Memory Design Automation Engineer — Frontend Kits & Flows

PERSOL SINGAPORE PTE. LTD.; Singapore; On-site; SGD 90,000 - 180,000; Full time

Job summary

PERSOL SINGAPORE PTE. LTD. is looking for a memory front-end engineer to lead the development of memory design kits, RTL models, and ATPG for the ASIC flow. You will optimize automation using Perl or Python and validate models with Synopsys and Mentor Graphics EDA tools.

Apply your Verilog expertise to ensure functional memory circuit correctness, collaborate with memory design and compiler teams, and support RTL, verification, and DFT groups to deliver robust front-end solutions.

Qualifications

• Bachelor’s degree or higher in Electrical/Electronics engineering or related field.
• Knowledge of high-performance SRAM/ROM and VLSI design is a plus.
• Proficiency in Perl, Shell, Python, C/C++ and AI/ML basics is advantageous.
• Solid understanding of Verilog (behavioral, RTL, synthesizable) required.
• Familiarity with Liberty timing syntax is a plus.
• Experience with EDA tools (VCS, QuestaSim, NC) required.
• DFT: Tessent, Fastscan; Synthesis: Design Compiler, Genus; Simulation: VCS, QuestaSim, NC; STA: PrimeTime.
• Strong scripting and flow automation skills; good team collaboration.

Responsibilities

• Lead development and coding of front-end design kits, memory RTL and ATPG models.
• Create and optimize automation flows using Perl or Python to improve efficiency.
• Use EDA tools from Synopsys and Mentor Graphics to validate models.
• Stay updated on modeling standards and tool vendor advancements.
• Ensure functional correctness of memory circuits against models.
• Collaborate with memory design and compiler teams to deliver front-end kits.
• Troubleshoot model issues with RTL designers, verification teams, DFT, and tool vendors.

Skills

Perl

Python

C/C++

Verilog

Team player

Scripting

Education

Bachelor’s Degree or higher in Electrical Engineering or Electronics Engineering

Tools

VCS

QuestaSim

NC

Design Compiler

Genus

PrimeTime

Tessent

Fastscan

Job description

PERSOL SINGAPORE PTE. LTD. is looking for a memory front-end engineer to lead the development of memory design kits, RTL models, and ATPG for the ASIC flow. You will optimize automation using Perl or Python and validate models with Synopsys and Mentor Graphics EDA tools.

Apply your Verilog expertise to ensure functional memory circuit correctness, collaborate with memory design and compiler teams, and support RTL, verification, and DFT groups to deliver robust front-end solutions.