Memory Design Automation - Memory Modeling

PERSOL; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

PERSOL Singapore is seeking a front-end memory design engineer to lead development of memory design kits, RTL models, and related views for ASIC flows.

You will automate workflows with Perl and Python, validate models using Synopsys and Mentor graphics tools, and collaborate with memory design and compiler teams to ensure accuracy and performance.

Qualifications

• Bachelor’s degree in Electrical/Electronics Engineering or related field.
• Knowledge of high performance SRAM/ROM and VLSI design; experience with EDA tools is helpful.
• Proficient in Perl, Shell, Python, and C/C++; AI/ML knowledge is a plus.
• Strong understanding of Verilog (behavioral, RTL, synthesizable).
• Experience with EDA tools such as VCS and NC is required.
• DFT tools: Tessent, Fastscan; Synthesis: Design Compiler, Genus; STA: PrimeTime.

Responsibilities

• Lead development and coding of front-end design kits for memory.
• Create automation flows and scripts to enhance workflow efficiency.
• Validate memory models using Synopsys and Mentor Graphics tools.
• Maintain up-to-date knowledge of modeling standards and EDA advancements.
• Ensure functional correctness of memory circuits against memory models.
• Collaborate with memory design and compiler teams to deliver front-end kits.
• Troubleshoot model issues with RTL designers, verification, DFT teams, and tool vendors.

Skills

Perl

Shell

Python

C/C++

AI/ML

Verilog

Scripting

Team player

Education

Bachelor’s Degree in Electrical/Electronic Engineering or related field

Tools

VCS

NC

QuestaSim

Design Compiler

Genus

PrimeTime

Tessent

Fastscan

Job description

Job Description

• Lead the development and coding of front-end design kits, including memory RTL models, ATPG models, and other views essential for ASIC design flow.

• Create and optimize automation flows and scripts using Perl or Python to enhance workflow efficiency and ensure model accuracy.

• Utilize EDA tools from vendors such as Synopsys and Mentor Graphics to validate model correctness.

• Maintain up-to-date knowledge of current modeling standards and advancements from EDA tool vendors to enhance memory IP performance and meet the latest ASIC design flow requirements.

• Ensure the functional correctness of memory circuits by validating them against memory models.

• Collaborate with the memory design team and compiler development team to deliver comprehensive memory front-end design kits.

• Troubleshoot and resolve model issues in collaboration with RTL designers, design verification teams, DFT teams, and tool vendors.

Job Requirements

• Bachelor’s Degree or higher in Electrical Engineering, Electronics Engineering, or related discipline.

• Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage. Experience with EDA tools will be helpful.

• Proficient with Perl, Shell, Python, C/C++ languages, knowledge with AI machine learning algorithm and infrastructure is an added advantage.

• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.

• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.

• Understanding of liberty timing syntax is a plus.

• Knowledge and experience with EDA simulation tools such as VCS, NC is required.

• Experience with EDA tools will be helpful:

• DFT: Logicvision, Tessent, Fastscan

• Synthesis: Design compiler, Genus

• Simulation tools:VCS, QuestaSim, NC

• STA tools such as PrimeTime

• Good scripting and flow automation skills, in Perl or Python.

• A team player, meticulous, able to work and learn independently are important attributes for this job.