AI ASIC Memory Compiler, Technical Manager

PERSOL SINGAPORE PTE. LTD.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

PERSOL SINGAPORE PTE. LTD. is seeking a memory design automation engineer to deliver robust memory solutions and develop Memory Compiler automation flows in Singapore. The role emphasizes high performance, low power SRAM/ROM and collaboration with global memory design teams.

The candidate should have 8+ years in memory/VLSI, strong programming in Perl/Shell/Python/C/C++, Verilog, and experience with EDA tools like VCS, QuestaSim, NC and PrimeTime.

Qualifications

• 8+ years of relevant experience in memory design/ASIC environments.
• Proficiency in Perl, Shell, Python and C/C++; Verilog expertise required.
• Strong understanding of Liberty timing syntax and EDA tools.
• Experience with memory design/Memory Compiler automation is a plus.

Responsibilities

• Deliver robust memory solutions for ASIC flows.
• Develop Memory Compiler automation flows to improve design efficiency.
• Create behavioral, FPGA, timing, and DFT simulation models.
• Debug and optimize SRAM models for ASIC design flows.

Skills

Perl

Shell

Python

C/C++

Verilog

Liberty timing syntax

AI/ML knowledge

Tools

VCS

QuestaSim

NC

PrimeTime

Design compiler

Genus

Logicvision

Tessent

Fastscan

Job description

Job Description

In the Memory Design Automation team, we work seamlessly with worldwide memory design teams to deliver high performance, low power and small area in-house memories design kits and design flows under advanced technology nodes. We are looking for candidate to join us as memory design automation engineer for the delivery of robust memory and development of Memory Compiler automation flow.

• Delivering robust memory solutions.
• Developing Memory Compiler automation flows.
• Creating behavioral, FPGA, timing, and DFT simulation models.
• Debugging andoptimizing SRAM models for ASIC design flows.

Job Requirements

• Knowledge of high performance, low power SRAM/ROM and VLSIdesign is an added advantage. Experience with EDA tools will be helpful.
• With min. 8 years of relevant experience in similar industry.
• Proficient with Perl, Shell, Python, C/C++ languages, knowledgewith AI machine learning algorithm and infrastructure is an added advantage.
• Good understanding of verilog syntax and its various aspects,such as behavioral, RTL and synthesizable verilog is a must.
• Good understanding of liberty timing syntax.
• Knowledge and experience with EDA simulation tools such as VCS,NC is required.
• Experience with EDA tools will be helpful:
• DFT: Logicvision, Tessent, Fastscan
• Synthesis: Design compiler, Genus
• Simulation tools:VCS, QuestaSim, NC
• STA tools such as PrimeTime