AI ASIC Memory Compiler Engineer

PERSOL SINGAPORE PTE. LTD.; Singapore; On-site; SGD 67,000 - 134,000; Full time

Job summary

MediaTek is seeking a Memory Design Automation Engineer to join the Memory Design Automation team. You will work with global memory design teams to deliver high-performance, low-power, small-area memories design kits and design flows on advanced nodes.

Responsibilities include delivering robust memory solutions, developing Memory Compiler automation flows, and building behavioral, FPGA, timing, and DFT models while debugging SRAM models for ASIC flows.

Qualifications

• Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage.
• Experience with EDA tools will be helpful.
• Proficient with Perl, Shell, Python, C/C++ languages; AI/ML experience is an added advantage.
• Good understanding of Verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.
• Good understanding of liberty timing syntax.
• Knowledge and experience with EDA simulation tools such as VCS, NC is required.

Responsibilities

• Delivering robust memory solutions.
• Developing Memory Compiler automation flows.
• Creating behavioral, FPGA, timing, and DFT simulation models.
• Debugging and optimizing SRAM models for ASIC design flows.

Skills

Perl

Shell

Python

C/C++

Verilog

AI/ML basics

Good communication in English

Tools

VCS

QuestaSim

NC

PrimeTime

Design Compiler

Genus

Tessent

Fastscan

Job description

Job Responsibilities:

At MediaTek's Memory Design Automation team, we work seamlessly with worldwide memory design teams to deliver high performance, low power and small area in-house memories design kits and design flows under advanced technology nodes. We are looking for candidate to join us as memory design automation engineer for the delivery of robust memory and development of Memory Compiler automation flow.

• Delivering robust memory solutions.
• Developing Memory Compiler automation flows.
• Creating behavioral, FPGA, timing, and DFT simulation models.
• Debugging and optimizing SRAM models for ASIC design flows.

Requirements:

• Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage.
• Experience with EDA tools will be helpful.
• Proficient with Perl, Shell, Python, C/C++ languages, knowledge with AI machine learning algorithm and infrastructure is an added advantage.
• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.
• Good understanding of liberty timing syntax.
• Knowledge and experience with EDA simulation tools such as VCS, NC is required.
• Experience with EDA tools will be helpful:
  • DFT: Logicvision, Tessent, Fastscan
  • Synthesis: Design compiler, Genus
  • Simulation tools:VCS, QuestaSim, NC
  • STA tools such as PrimeTime

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