We are developing a next-generation 2D semiconductor technology platform targeting ultra-scaled logic and memory applications beyond conventional silicon limits. Our approach emphasizes device–circuit co-design, connecting atomistic transport physics to circuit-level performance projections.
As a Device & Circuit Simulation Engineer, you will be responsible for bridging ultra-scaled device simulations and functional circuit evaluation. You will work across multiple simulation layers, from quantum transport (NEGF) and TCAD to compact modeling and SPICE-based circuit analysis, enabling credible technology benchmarking for logic gates, SRAM, and oscillators. This role is critical for guiding device architecture decisions and demonstrating the system-level impact of emerging 2D devices.
Responsibilities
- Perform ultra-scaled device simulations for advanced FET architectures using quantum transport methods (e.g., NEGF, QuantumATK or equivalent); atomistic or semi-classical approaches as appropriate
- Analyze short-channel effects, contact-limited transport, electrostatics, and scattering mechanisms in 2D devices
- Extract device trends (I–V, SS, gm, Rc, capacitance) suitable for higher-level modeling
TCAD & Technology Projection
- Conduct TCAD simulations to explore device scaling, geometry, and process sensitivity
- Calibrate TCAD models using inputs and trends from quantum/atomistic simulation
- Support technology projection studies for advanced nodes (e.g., GAA, CFET, stacked or vertical architectures)
Compact Modeling & TCAD-to-SPICE Flow
- Develop simplified compact models or parameterized abstractions from device/TCAD results
- Enable TCAD-to-SPICE flows for circuit-level simulation and comparison
- Validate consistency between device physics, TCAD behavior, and circuit-level response
Circuit-Level Simulation & Analysis
- Perform circuit simulations for basic logic and memory structures, including inverters, NAND/NOR gates, ring oscillators, SRAM cells
- Evaluate circuit-level metrics such as delay, power, noise margin, and stability
- Correlate circuit performance with device non-idealities and variability
Documentation & Collaboration
- Document simulation methodologies, assumptions, and limitations clearly
- Prepare internal reports, benchmarking summaries, and projection data for technical reviews
- Collaborate closely with materials, device fabrication, and circuit demo teams
Minimum Qualifications
- Master’s degree or PhD in Electrical Engineering, Materials Science, Applied Physics, or a related field
- Strong background in semiconductor device physics, particularly short-channel and nanoscale effects
- Hands-on experience with device simulation tools (quantum transport and/or TCAD)
- Familiarity with SPICE or TCAD-based circuit simulation and basic digital circuit operation
- Ability to translate device-level behavior into circuit-relevant metrics
Preferred Qualifications
- Experience with QuantumATK, NEGF-based simulators, or atomistic device modeling
- Experience with TCAD tools (Sentaurus, Silvaco) and scaling studies
- Exposure to compact modeling, Verilog-A, or parameterized SPICE models
- Prior work on emerging devices (2D semiconductors, GAA, CFET, beyond-CMOS concepts)
- Experience with SRAM or RO-based technology benchmarking
- Publications in IEDM, VLSI, IEEE TED, or related conferences/journals
- Proficiency in Python, MATLAB, or similar tools for data analysis and automation
What this Role is NOT
- Not a full-custom IC layout or a backend design role
- Not a sign-off CMOS design or large-scale SRAM compiler position
- Focus is on technology projection and device–circuit correlation, not product-level IC implementation