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JAC Recruitment Consultant is seeking a highly skilled 2.5D/3D Assembly Engineer to support development and implementation of advanced semiconductor packaging and integration technologies in Singapore. You will focus on wafer-level packaging and optimization of 2.5D/3D assembly processes.
The role involves reliability engineering, DFM/DFT collaboration, and close work with partners to deliver next-generation packaging solutions for high-performance semiconductor applications.
We are seeking a highly skilled 2.5D / 3D Assembly Engineer to support the development and implementation of advanced semiconductor packaging and integration technologies. This role will focus on wafer-level packaging, 2.5D/3D assembly processes, package design optimization, reliability engineering, and advanced technology development.
The successful candidate will play a key role in driving innovation, improving assembly methodologies, collaborating with external partners, and developing next-generation packaging solutions for advanced semiconductor applications.
Lead the development and optimization of advanced semiconductor packaging and assembly technologies, including 2.5D and 3D integration.
Support package design, assembly process development, and Design for Manufacturing (DFM) and Design for Test (DFT) initiatives.
Perform thermo-mechanical, electrical, and reliability analysis using simulation and modeling tools.
Investigate and resolve packaging, assembly, and reliability challenges across various operating environments.
Collaborate with cross-functional teams, suppliers, and manufacturing partners to drive technology development and process improvements.
Conduct failure analysis, root-cause investigations, and reliability assessments to improve product performance.
Support the introduction of new materials, packaging technologies, and assembly methodologies.
Contribute to technical documentation, design guidelines, and continuous improvement initiatives.
Master's or PhD in Mechanical Engineering, Materials Science, Physics, Semiconductor Packaging, Micro/Nanofabrication, or a related discipline.
Strong hands-on experience in semiconductor assembly, packaging, or advanced integration technologies.
Experience with wafer-level packaging, 2.5D/3D packaging, and advanced assembly processes.
Knowledge of semiconductor package structures, materials, manufacturing processes, and reliability considerations.
Familiarity with CAD tools and thermo-mechanical simulation methodologies.
Experience with Finite Element Modeling (FEM) for thermal, mechanical, or electrical analysis.
Strong understanding of assembly-related failure mechanisms and reliability engineering.
Excellent analytical, troubleshooting, and engineering problem-solving skills.
Solid understanding of material properties, physics fundamentals, and package behavior across varying environmental conditions.
Experience developing Process Design Kits (PDKs) or packaging design flows.
Knowledge of Through-Silicon Via (TSV), silicon processing, and thin-film technologies.
Experience with cryogenic testing or low-temperature electro-mechanical characterization.
Exposure to high-voltage or power semiconductor packaging qualification.
Background in process engineering, manufacturing engineering, or advanced packaging development.