Senior Asic Verification Engineer - Hbm & Systemverilog

Synopsys; Porto; Presencial; EUR 70 000 - 110 000; Tempo integral

Resumo da oferta

Synopsys, Inc. in Porto, Portugal seeks a highly skilled Verification Engineer to lead ASIC digital verification with HBM protocol expertise.

You will design verification plans, build testbenches with SystemVerilog and UVM, and collaborate with design teams to meet specifications.

You will debug complex ASIC issues, optimize verification environments, and mentor junior engineers, contributing to high-performance silicon validation.

Qualificações

• Experience in ASIC digital verification with HBM protocol.
• Proficient with SystemVerilog and UVM testbenches.
• Lead verification plans and debug complex issues.

Responsabilidades

• Design verification plans and lead testbench development.
• Build testbenches with SystemVerilog and UVM.
• Collaborate with design teams to meet specifications and optimize environments.
• Mentor junior engineers and contribute to silicon validation quality.

Conhecimentos

ASIC verification

HBM protocol

Mentoring

Debugging

Team collaboration

Ferramentas

SystemVerilog

UVM

Descrição da oferta de emprego

Synopsys, Inc. in Porto, Portugal seeks a highly skilled Verification Engineer to lead ASIC digital verification with HBM protocol expertise. You will design verification plans, build testbenches with SystemVerilog and UVM, and collaborate with design teams to meet specifications. You will debug complex ASIC issues, optimize verification environments, and mentor junior engineers, contributing to high-performance silicon chip validation and overall product quality.

Senior Asic Verification Engineer - Hbm & Systemverilog Senhora Da Hora, Portuguese Republic, PT