Senior ASIC Digital Architect for HPC Memory IP

Synopsys, Inc.; Porto; Remote; EUR 110.000 - 170.000; Vollzeit

Benefits dieser Stelle

Health benefits

Wellness programs

Financial rewards

Zusammenfassung

Synopsys, Inc. is seeking an experienced ASIC design leader to drive micro-architecture and RTL for next‑generation memory IP used in HPC and AI infrastructure. You will balance performance, power, area, and timing while collaborating with physical design and verification teams.

The role requires deep knowledge of DDR/HBM protocols, mixed-signal co-design, and a track record of successful tape-outs, with mentorship experience to grow a strong engineering team.

Qualifikationen

• Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of hands-on ASIC digital design experience with tape-out.
• Deep expertise in high-speed communication protocols (DDR, HBM).
• Strong knowledge of clock domain crossing (CDC) and reset domain crossing (RDC).
• Experience with synthesis flows and timing closure.

Aufgaben

• Define micro-architecture for mixed-signal IP blocks for HPC applications.
• Develop RTL for high-speed digital blocks including DDR and HBM interfaces.
• Model circuit behavior for analog/mixed-signal components for co-design and validation.
• Refine synthesis constraints with physical design and timing teams to meet targets.
• Run code quality checks (Lint, CDC, RDC) and catch issues early.
• Evaluate design trade-offs and propose solutions aligned with product goals.
• Mentor engineers by reviewing designs and guiding technical decisions.

Kenntnisse

High-speed interfaces

RTL design

CDC/RDC analysis

Synthesis

Engineering mentorship

Ausbildung

Master's degree in Electrical/Electrical Engineering or Computer Engineering

Tools

Synthesis tools

Jobbeschreibung

Synopsys, Inc. is seeking an experienced ASIC design leader to drive micro-architecture and RTL for next‑generation memory IP used in HPC and AI infrastructure. You will balance performance, power, area, and timing while collaborating with physical design and verification teams.

The role requires deep knowledge of DDR/HBM protocols, mixed-signal co-design, and a track record of successful tape-outs, with mentorship experience to grow a strong engineering team.