Senior Principal Engineer: Silicon Signoff & Design

PeopleStrong; Hinoba-an; On-site; PHP 2,653,000 - 4,642,000; Full time

Job summary

LTST-L&T Semiconductor Technologies Limited in Bengaluru seeks a Senior Principal Engineer to lead physical verification sign-off for SoCs, cores and blocks. You will own flows, drive tool adoption, and guide teams to deliver tapeout-ready databases.

You will provide expert technical direction, coordinate with EDA vendors, and resolve critical PV issues impacting schedules and silicon quality. Bachelor of Technology is required, with 18–24 years of experience.

Qualifications

• Bachelor of Technology (BTech) degree required.
• 18-24 years of relevant experience preferred.

Responsibilities

• Oversee physical verification of SoCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout readiness.
• Own and drive physical verification and signoff methodologies, flows, automation, and execution across SoC/Block/IP levels.
• Drive the final signoff process to deliver a clean, tapeout-ready database and governance of tools/flows for mask generation.
• Provide technical direction, estimation, planning and execution leadership to ensure predictable project delivery.
• Offer technical guidance to resolve complex sign-off issues related to physical verification.
• Work hands-on to resolve critical design and physical verification issues impacting schedules and quality.
• Collaborate with EDA tool vendors to meet tool feature, enhancement and support needs.
• Evaluate and recommend new tools and methodologies for physical design and sign-off.
• Lead efforts to reduce cycle time and improve design quality and efficiency.

Skills

Physical Design

Sign-off

Automation

Leadership

Project planning

Education

BTech

Tools

EDA Tools

Job description

LTST-L&T Semiconductor Technologies Limited in Bengaluru seeks a Senior Principal Engineer to lead physical verification sign-off for SoCs, cores and blocks. You will own flows, drive tool adoption, and guide teams to deliver tapeout-ready databases.

You will provide expert technical direction, coordinate with EDA vendors, and resolve critical PV issues impacting schedules and silicon quality. Bachelor of Technology is required, with 18–24 years of experience.