Lead DFT Architect for ASIC Testability

Synopsys, Inc.; Hinoba-an; On-site; PHP 990,000 - 1,319,000; Full time

Job summary

Synopsys, Inc. in Bangalore seeks an experienced ASIC DFT leader to drive scan insertion, ATPG, and STA flows for complex IP designs. You will lead a team of DFT engineers and collaborate with RTL and verification teams to embed DFT early in the design cycle.

You will mentor engineers, resolve DFT issues with Spyglass DFT, and push AI-enabled DFT flows to boost testability, reliability, and time-to-market across AI, automotive, and other high-impact sectors.

Qualifications

• BS/MS in Electrical Engineering or Electronics and Communications Engineering with 8+ years of relevant experience.
• Past experience leading a team for DFT execution of IP projects and stakeholders across PM, design, verification, and implementation teams.
• Proven experience in DFT methodologies, including scan insertion and ATPG for complex ASIC designs.
• Proficiency with Spyglass DFT and scan STA analysis suites.
• Some experience using AI tools for DFT tasks and automation of design/test flows.

Responsibilities

• Lead and drive execution of scan insertion and ATPG flows for complex IP designs along with a team of DFT engineers.
• Work closely with RTL and Verification teams to integrate DFT requirements early in the design cycle.
• Analyze/resolve DFT-related issues using Spyglass DFT, ensuring robust test coverage and manufacturability.
• Guide team and perform scan STA to validate timing closure and optimize testability paths.
• Use AI tools/flow for DFT tasks to improve efficiency and collaborate with cross-functional teams to define best practices.

Skills

DFT leadership

Scan insertion

ATPG

Spyglass DFT

AI tools

Team mentorship

Cross-functional collaboration

Education

Electrical Engineering BS/MS

Tools

Spyglass DFT

scan STA

Job description

Synopsys, Inc. in Bangalore seeks an experienced ASIC DFT leader to drive scan insertion, ATPG, and STA flows for complex IP designs. You will lead a team of DFT engineers and collaborate with RTL and verification teams to embed DFT early in the design cycle.

You will mentor engineers, resolve DFT issues with Spyglass DFT, and push AI-enabled DFT flows to boost testability, reliability, and time-to-market across AI, automotive, and other high-impact sectors.