Staff Digital Implementation Engineer

Xinyx Design; Manila; On-site; PHP 900,000 - 1,300,000; Full time

Job summary

Xinyx Design seeks a Staff Digital Implementation Engineer to drive complex ASIC implementation from synthesis to signoff, defining methodologies and guiding teams to design closure with strong PPA optimization.

The role requires deep expertise in digital flows and hands-on use of Synopsys ICC2, Cadence Innovus, and PrimeTime, plus scripting with TCL/Perl/Python and DFT familiarity.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering (Master’s/PhD a plus).
• 10+ years of experience in ASIC digital implementation with leadership of tapeouts.
• Expertise in synthesis, PnR, STA and signoff methodologies.

Responsibilities

• Lead and optimize synthesis, place and route, and timing closure for large-scale designs ensuring PPA targets are met.
• Drive static timing analysis, signal integrity checks, and power optimization across corners/modes.
• Collaborate with RTL, verification and physical design teams to resolve implementation challenges.
• Define and improve digital implementation methodologies for efficiency and best practices.
• Leverage EDA tools (ICC2, Innovus, PrimeTime) to drive implementation quality.
• Lead debugging of DRC/LVS violations, timing bottlenecks, and physical design constraints.
• Document and maintain best practices for design implementation processes.
• Provide technical mentorship to engineers at all levels.

Skills

Digital implementation

Leadership

Scripting ( TCL/Perl/Python )

EDA tool proficiency

Low-power design

Education

Bachelor’s degree in Electrical or Computer Engineering

Master’s degree or PhD (preferred)

Tools

Synopsys ICC2

Cadence Innovus

PrimeTime

Job description

Job Summary:

The Staff Digital Implementation Engineer is a technical leader responsible for driving complex ASIC implementation from synthesis to signoff. This role involves defining methodologies, solving high-impact design challenges, and providing technical guidance across teams. The ideal candidate has deep expertise in digital implementation flows and a strong ability to optimize PPA while ensuring design closure.

Key Responsibilities:

• Digital Design Implementation: Lead and optimize synthesis, place and route, and timing closure efforts for large-scale designs, ensuring power, performance, and area (PPA) targets are met.
• Timing Closure: Drive static timing analysis, signal integrity checks, and power optimization across multiple corners and modes.
• Collaboration: Partner with RTL, verification, and physical design teams to resolve implementation challenges and enhance design convergence.
• Methodology Development: Define and improve digital implementation methodologies, ensuring efficiency and best practices across projects.
• Tool Utilization: Leverage advanced features of EDA tools (e.g., Synopsys ICC2, Cadence Innovus, PrimeTime) to drive implementation quality.
• Debugging and Troubleshooting: Lead resolution of complex DRC/LVS violations, timing bottlenecks, and physical design constraints.
• Documentation: Establish and maintain best practices documentation for design implementation processes.
• Mentorship: Provide technical mentorship to engineers at all levels, fostering skill development and innovation within the team.

Key Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field. Master’s/PhD is a plus.
• 10+ years of experience in ASIC digital implementation, with a strong track record of leading design tape outs..
• Expertise in synthesis, PnR, STA, and signoff methodologies.
• Deep knowledge of EDA tools like Synopsys Design Compiler, Cadence Innovus, and PrimeTime.
• Hands-on experience with low-power design techniques and multi-corner signoff.
• Strong scripting and automation skills (TCL, Perl, Python).
• Familiarity with DFT insertion and verification methodologies.