Physical Design Engineer: RTL to GDS & Signoff

Altera Corporation; Hinoba-an; On-site; PHP 600,000 - 900,000; Full time

Job summary

Altera Corporation seeks a highly skilled engineer to drive full physical design flows from RTL to GDS for complex IP and SoC blocks. You will manage synthesis, place & route, floor planning, clock tree synthesis, and rigorous timing and power analyses.

The role requires strong expertise in EDA tools and signoff verification to ensure robust design closures. The candidate will optimize power, frequency, and area while contributing to methodology improvements and flow automation.

Qualifications

• Experience with physical design flow and RTL-to-GDS conversion.
• Proficiency in timing, power/clock distribution, reliability and P&G analyses.
• Familiarity with formal verification, STA, and signoff processes.

Responsibilities

• Perform physical design implementation from RTL to GDS for custom IP and SoC designs.
• Execute synthesis, place and route, clock tree synthesis, floor planning, STA, power integrity, and layout verification.
• Conduct verification and signoff including EDA-based checks and rules enforcement; analyze results and optimize parameters.

Skills

Physical design

Timing closure

Power analysis

Clock tree synthesis

Place & route

DFT

Synthesis

EDA tools

Tools

EDA tools

Job description

Altera Corporation seeks a highly skilled engineer to drive full physical design flows from RTL to GDS for complex IP and SoC blocks. You will manage synthesis, place & route, floor planning, clock tree synthesis, and rigorous timing and power analyses.

The role requires strong expertise in EDA tools and signoff verification to ensure robust design closures. The candidate will optimize power, frequency, and area while contributing to methodology improvements and flow automation.