Lead ASIC Verification Engineer & Testbench Architect

Synopsys, Inc.; Hinoba-an; On-site; PHP 2,309,000 - 4,288,000; Full time

Job summary

Synopsys, Inc. in Bangalore seeks a senior verification team lead to drive end-to-end IP verification for DesignWare cores. You will mentor engineers, design scalable SystemVerilog/UVM environments, and define test plans that cover corner cases and system interactions.

The role emphasizes signoff readiness, functional and code coverage, and collaboration with RTL and architecture teams to ensure robust verification across multiple product generations.

Qualifications

• 8+ years hands-on verification experience.
• Proven track record leading verification teams through IP project delivery.
• Strong SystemVerilog/UVM testbench development.
• Experience with DDR/LPDDR protocols is a plus.
• Ability to own end-to-end verification deliverables.
• Experience with AI-assisted verification tools is a plus.

Responsibilities

• Lead a verification team through full IP verification cycles, from test plan to coverage closure and signoff.
• Build and evolve SystemVerilog/UVM verification environments for DesignWare IP cores, scalable across product generations.
• Define test plans covering corner cases, protocol compliance, and system interactions; guide implementation.
• Write and debug testbenches, checkers, and assertions for serial interfaces and memory controllers.
• Analyze functional and code coverage to drive closure and adjust strategy in real time.
• Collaborate with RTL designers, digital architects, and circuit teams to align verification with design intent.
• Manage regression infrastructure and coordinate with infra teams for efficient cycles.

Skills

SystemVerilog/UVM

Verification leadership

Testbench development

Functional coverage

DDR/LPDDR protocols

Education

Bachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering

Tools

DDR/LPDDR protocols

Job description

Synopsys, Inc. in Bangalore seeks a senior verification team lead to drive end-to-end IP verification for DesignWare cores. You will mentor engineers, design scalable SystemVerilog/UVM environments, and define test plans that cover corner cases and system interactions.

The role emphasizes signoff readiness, functional and code coverage, and collaboration with RTL and architecture teams to ensure robust verification across multiple product generations.