Senior Design Verification Engineer

Lattice Semiconductor; Manila; On-site; PHP 781,200 - 1,227,600; Full time

Job summary

Lattice Semiconductor is seeking a skilled engineer in Manila, Philippines, with 6-10 years of Digital Design Verification experience. The role involves developing verification plans and collaborating with design engineers to ensure high-quality SoC verification.

Candidates should possess a degree in Computer Science or related fields and have experience with simulation tools like Cadence IES and Synopsys VCS. Strong communication and analytical skills are crucial for this position. All qualified candidates are welcome to apply.

Qualifications

• 6-10 years of Digital Design Verification experience.
• Skill in debugging and analyzing complex digital designs.
• Experience with HDL and HVL languages and methodologies.

Responsibilities

• Develop comprehensive verification plans and metrics.
• Verify design blocks and full chips using various verification methods.
• Collaborate with design engineers to deliver quality verification.

Skills

Digital Design Verification

Debugging complex digital designs

HDL and HVL languages

ASIC/FPGA/SoC verification

Simulation tools

Python

Perl

Shell scripting

Education

Bachelor's or Master's degree in Computer Science, Computer Engineering, Electronics, or Electrical Engineering

Tools

Cadence IES/XCELIUM

Synopsys VCS

Mentor’s Questa

Job description

Overview

Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists partnering with sales, marketing, and support teams to develop programmable logic solutions that transform the industry. The focus is on R&D, product innovation, and customer service with a commitment to excellence.

Accountabilities

• Develop comprehensive verification plans, clear metrics, and continuously measure progress throughout the project
• Verify design blocks, subsystems, and full chips using assertion-based verification, formal verification, directed tests, and randomized tests
• Understand specifications and use cases, and develop SystemVerilog and ‘C’ based testbenches in a UVM environment
• Design and develop testbench components such as Universal Verification Components, BFMs, and verification tools
• Define and design verification regression environments
• Perform functional coverage, RTL code coverage, assertion coverage, and gate-level simulations
• Collaborate with design engineers, IP developers, and SW developers to deliver high-quality SoC verification on aggressive time schedules
• Develop best practices and world‑class methods for SoC verification

Required Skills

• 6‑10 years of Digital Design Verification experience
• Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electronics, or Electrical Engineering
• Skill in debugging and analyzing complex digital designs
• Experience with HDL and HVL languages and methodologies
• Experience in ASIC/FPGA/SoC verification or development cycles
• Experience with simulation tools such as Cadence IES/XCELIUM, Synopsys VCS, or Mentor’s Questa
• Hands‑on experience in Python, Perl, or Shell scripting, TCL, and Make
• Strong communication, analytical, and documentation skills with the ability to interface with other groups or sites
• Keeping up to date on industry trends and verification technology development

Additional Information

This position requires a successful background and reference check and proof of the right to work in the Philippines.

Applications are welcome from all qualified candidates.