Senior Logic Design Engineer - AI Silicon with Tape-out Ownership

IC Resources; Eindhoven; On-site; EUR 110,000 - 140,000; Full time

Job summary

IC Resources is seeking a Senior/Staff Logic Design Engineer in Eindhoven to lead RTL development for advanced AI silicon. You will own key RTL blocks, translate architectural concepts to production-ready silicon, and work across front-end design, verification, and physical teams.

You will drive timing closure, PPA optimisation, low-power techniques, and gate-level verification, with a track record of successful ASIC tape-outs in complex SoCs.

Qualifications

• Experience in ASIC/SoC RTL design for complex processor/accelerator blocks.
• Strong knowledge of SystemVerilog/Verilog and microarchitectures.
• Familiarity with synthesis, timing closure and RTL design with awareness of AMBA protocols.

Responsibilities

• Translate architecture and ISA requirements into microarchitectural RTL.
• Design processor, accelerator and complex SoC blocks.
• Integrate internal and third-party IP and interface with verification, architecture and physical design teams.
• Support synthesis, timing closure and PPA optimisation.
• Drive CDC/RDC quality and sign-off.
• Implement low-power techniques including clock gating and power management.
• Support gate-level simulation, FPGA and emulation activities, and drive tape-out ownership.

Skills

ASIC/SoC RTL Design

SystemVerilog / Verilog

Microarchitecture

Synthesis & timing RTL

AMBA/AXI/AHB/APB

CDC / RDC

Tape-out experience

Tools

Synthesis tools

Gate-level simulation

FPGA emulation

Job description

IC Resources is seeking a Senior/Staff Logic Design Engineer in Eindhoven to lead RTL development for advanced AI silicon. You will own key RTL blocks, translate architectural concepts to production-ready silicon, and work across front-end design, verification, and physical teams.

You will drive timing closure, PPA optimisation, low-power techniques, and gate-level verification, with a track record of successful ASIC tape-outs in complex SoCs.