Senior RTL Design Engineer – AI Silicon Tape-out

Intellectual Capital Resources Ltd; Eindhoven; On-site; EUR 90,000 - 120,000; Full time

Job summary

Intellectual Capital Resources Ltd is seeking a Senior / Staff Logic Design Engineer for a groundbreaking AI silicon project in Eindhoven. You will own key RTL blocks, convert architectural concepts into production-ready silicon, and work across front-end design, verification and physical implementation.

You will drive low-power techniques and sign-off readiness, collaborating with architecture, verification and backend teams to deliver high-performance AI compute blocks and accelerator

Qualifications

• 5+ years in ASIC / SoC RTL design.
• Strong SystemVerilog or Verilog skills.
• Experience with processors, accelerators or complex SoCs.
• Solid microarchitecture know-how.
• Synthesis and timing-aware RTL design experience.
• Knowledge of AMBA/AXI/AHB/APB.
• CDC / RDC expertise.
• Hands-on low-power design experience.
• Gate-level simulation and debugging.
• At least one ASIC tape-out.
• Experience owning design blocks through development.

Responsibilities

• Develop synthesizable SystemVerilog / Verilog RTL.
• Translate architecture/ISA into microarchitecture.
• Design processor, accelerator and complex SoC blocks.
• Integrate internal and third-party IP.
• Collaborate with verification, architecture and physical design.
• Support synthesis, timing closure and PPA optimization.
• Drive CDC / RDC quality and sign-off.
• Implement low‑power techniques including clock/power gating.
• Support gate-level simulation, FPGA and emulation.
• Own design blocks through tape-out.

Skills

ASIC / SoC RTL Design

SystemVerilog / Verilog

Microarchitecture

Processor / Accelerator / SoC

Synthesis & timing-aware RTL

AMBA / AXI / AHB / APB

CDC / RDC

Low-power design

Gate-level simulation & debugging

ASIC tape-out

Design block ownership

Job description

Intellectual Capital Resources Ltd is seeking a Senior / Staff Logic Design Engineer for a groundbreaking AI silicon project in Eindhoven. You will own key RTL blocks, convert architectural concepts into production-ready silicon, and work across front-end design, verification and physical implementation.

You will drive low-power techniques and sign-off readiness, collaborating with architecture, verification and backend teams to deliver high-performance AI compute blocks and accelerator