Senior ASIC Digital Design Engineer RTL, Tape-out, Quantum

Rotterdam Innovation City; Netherlands; Remote; EUR 120,000 - 180,000; Full time

Job summary

Qblox is seeking a senior ASIC Design Engineer to join our quantum computing control stack. You will own digital logic, contribute to architectural decisions, and drive front-end flows from RTL coding to initial synthesis, collaborating across analog, digital verification, and embedded software teams.

The role requires 8+ years in digital design within an R&D or fabless environment, strong VHDL/Verilog skills, and experience with AMBA protocols and scripting for automation.

Qualifications

• Experience: 8+ years as a digital design engineer in R&D or fabless ASIC environments.
• RTL coding with VHDL/Verilog and IP development.
• Strong experience with front-end EDA tools and AMBA AXI/AHB protocols.
• Knowledge of STA constraints and timing closure methods.
• Familiarity with analog/mixed-signal chips or IP.
• Proficient in Python, Tcl, Shell for automation and Git for version control.
• Excellent communication and collaboration skills.

Responsibilities

• Deconstruct requirements and design robust, high‑performance digital logic and IP blocks.
• Drive front-end ASIC flow: RTL coding, linting, CDC analysis, initial synthesis.
• Collaborate on verification with self-checking testbenches and top-level UVM environments.
• Propose innovative architectural changes and power-saving strategies.
• Act as core technical sparring partner to a diverse engineering team.

Skills

VHDL/Verilog

RTL coding

Digital design

AMBA AXI/AHB

Static timing

Analog/Mixed-signal

Scripting

Git

UVM

DFT

MATLAB/Simulink

DSP

Quantum interest

Job description

Qblox is seeking a senior ASIC Design Engineer to join our quantum computing control stack. You will own digital logic, contribute to architectural decisions, and drive front-end flows from RTL coding to initial synthesis, collaborating across analog, digital verification, and embedded software teams.

The role requires 8+ years in digital design within an R&D or fabless environment, strong VHDL/Verilog skills, and experience with AMBA protocols and scripting for automation.