Senior ASIC Design Engineer - Digital IP & Tapeouts

Entangled Future; Delft; Híbrido; EUR 90.000 - 120.000; Jornada completa

Descripción de la vacante

Qblox in Delft, Netherlands is seeking a senior ASIC Design Engineer to architect and implement high‑performance digital logic and IP. You will drive RTL coding in Verilog/VHDL, lead tape-outs, and collaborate with mixed‑signal, verification, and embedded software teams.

Bring 8+ years in digital design, R&D or fabless ASIC, deep RTL knowledge, and a track record of silicon deliveries. You will influence architecture, power‑saving strategies, and engineering processes in a fast‑growing quantum

Formación

• 8+ years as a digital design engineer in an R&D or fabless ASIC environment.
• Deep fundamental knowledge of digital design, IP development, and RTL coding with VHDL/Verilog.

Responsabilidades

• Architect and implement robust, high-performance digital logic and IP blocks.
• Drive RTL coding, linting, clock-domain crossing (CDC) analysis, and initial synthesis; collaborate on top-level UVM environments with verification.
• Propose innovative changes to chip architecture, power-saving strategies, and team methodologies.
• Act as a core technical sparring partner to a diverse engineering team across analog, digital verification, embedded software, and physics.

Conocimientos

RTL coding

VHDL/Verilog

Digital design

Tape-out

Descripción del empleo

Qblox in Delft, Netherlands is seeking a senior ASIC Design Engineer to architect and implement high‑performance digital logic and IP. You will drive RTL coding in Verilog/VHDL, lead tape-outs, and collaborate with mixed‑signal, verification, and embedded software teams.

Bring 8+ years in digital design, R&D or fabless ASIC, deep RTL knowledge, and a track record of silicon deliveries. You will influence architecture, power‑saving strategies, and engineering processes in a fast‑growing quantum