Senior/Staff ASIC Design Engineer

IC Resources; Eindhoven; On-site; EUR 110,000 - 140,000; Full time

Job summary

IC Resources is seeking a Senior/Staff Logic Design Engineer in Eindhoven to lead RTL development for advanced AI silicon. You will own key RTL blocks, translate architectural concepts to production-ready silicon, and work across front-end design, verification, and physical teams.

You will drive timing closure, PPA optimisation, low-power techniques, and gate-level verification, with a track record of successful ASIC tape-outs in complex SoCs.

Qualifications

• Experience in ASIC/SoC RTL design for complex processor/accelerator blocks.
• Strong knowledge of SystemVerilog/Verilog and microarchitectures.
• Familiarity with synthesis, timing closure and RTL design with awareness of AMBA protocols.

Responsibilities

• Translate architecture and ISA requirements into microarchitectural RTL.
• Design processor, accelerator and complex SoC blocks.
• Integrate internal and third-party IP and interface with verification, architecture and physical design teams.
• Support synthesis, timing closure and PPA optimisation.
• Drive CDC/RDC quality and sign-off.
• Implement low-power techniques including clock gating and power management.
• Support gate-level simulation, FPGA and emulation activities, and drive tape-out ownership.

Skills

ASIC/SoC RTL Design

SystemVerilog / Verilog

Microarchitecture

Synthesis & timing RTL

AMBA/AXI/AHB/APB

CDC / RDC

Tape-out experience

Tools

Synthesis tools

Gate-level simulation

FPGA emulation

Job description

Senior / Staff Logic Design Engineer – AI Silicon

Are you an experienced RTL Design Engineer who wants to work on genuinely new processor technology rather than another incremental SoC update?

I’m working with a fast-growing semiconductor company in Eindhoven developing a new generation of AI compute and accelerator silicon. The team is building highly complex processor and SoC technology from the ground up, with a strong focus on performance, power efficiency and scalable AI workloads.

They are now looking for a Senior / Staff Logic Design Engineer to take ownership of key RTL blocks and help turn architectural concepts into production-ready silicon.

What you’ll be doing

You’ll work across the full front-end design flow, including:

Translating architecture and ISA requirements into microarchitecture

Designing processor, accelerator and complex SoC blocks

Integrating internal and third-party IP

Working closely with verification, architecture and physical design teams

Supporting synthesis, timing closure and PPA optimisation

Driving CDC / RDC quality and sign-off

Implementing low-power techniques including clock gating, power gating and memory power management

Supporting gate-level simulation, FPGA and emulation activity

Taking real ownership of design blocks through to tape-out

What they’re looking for

You’ll ideally have:

5+ years of ASIC / SoC RTL Design experience

Strong SystemVerilog or Verilog

Experience with processors, accelerators or complex SoCs

Strong microarchitecture experience

Experience with synthesis and timing-aware RTL design

Good knowledge of AMBA / AXI / AHB / APB

Strong CDC / RDC expertise

Gate-level simulation and debugging experience

At least one successful ASIC tape-out

Experience owning one or more design blocks through the development cycle

Why this is interesting

This is a chance to join a semiconductor company at a genuinely exciting point in its growth, while the core architecture and silicon platform are still being built.

You won’t be joining a huge team where your work disappears into one tiny corner of the chip. You’ll have meaningful ownership, work closely with architecture and verification, and contribute directly to the development of advanced AI processor and accelerator technology.

For someone who enjoys RTL design, processor architecture, complex SoCs and high-performance silicon, this is a particularly strong opportunity in the Eindhoven semiconductor market.

If you’re a Senior RTL Design Engineer, Staff ASIC Design Engineer, SoC Design Engineer, Processor Design Engineer or Logic Design Engineer based in the Netherlands or interested in relocating to Eindhoven, please get in touch.