Analog Layout Engineer

Chipright; Netherlands; On-site; EUR 70,000 - 100,000; Full time

Job summary

Chipright seeks highly motivated Analog Layout development engineer to work within a team of experienced engineers on 22 nanometer technology. The role requires 5+ years in Analog Layout, high-speed SERDES layout, and deep sub-micron CMOS expertise.

Proficiency withSynopsys and Cadence tools is essential, with strong architectural influence and robust debugging skills. You will engage in floor planning, power routing, ESD design, and comprehensive physical verification, collaborating with tool

Qualifications

• 5+ years’ minimum experience in Analog Layout.
• Experience in High Speed Layout of SERDES.
• Experience in Layout of blocks such as PLLs, Transceivers, Receivers.
• Experience working on deep sub-micron CMOS (28nm or less).
• Proficient with Synopsys & Cadence tools.
• Ability to influence the architecture level and design to ensure layout is achievable.
• Experience with Floor Planning, Power Routing and ESD level design.
• Experience with Place & Route, Layout Finishing.
• Experience with DRC and all aspects of Physical Verification.
• Experience in working with EDA tool suppliers to yield best results.
• Strong debug & problem-solving skills.
• Educated to degree level with excellent analytical, communication and documentation skills.

Skills

Analog Layout

SerDes Layout

Floor Planning & Power Routing

Physical Verification

EDA Tools Proficiency

Troubleshooting & Debugging

Communication & Documentation

Education

Electrical Engineering Degree

Tools

Synopsys

Cadence

Place & Route

Job description

Analog Layout Engineer (22nm deep micron CMOS technology)

Chipright seeks highly motivated and experienced Analog Layout development engineer to work within a team of highly experienced engineers on 22 nanometer technology.

• 5+ years’ minimum experience in Analog Layout
• Experience in High Speed Layout of SERDES
• Experience in Layout of blocks such as PLLs, Transceivers, Receivers
• Experience working on deep sub-micron CMOS (28nm or less)
• Proficient with Synopsys & Cadence tools
• Ability to influence the architecture-level and design to ensure design layout can be achieved
• Experience with Floor Planning, Power Routing and ESD level design
• Experience with Place & Route, Layout Finishing
• Experience with Design Rule Checking (DRC) and all aspects of Physical Verification
• Experience in working with EDA tool suppliers to yield the best results from their tools
• Strong debug & problem-solving skills
• Educated to degree level with excellent analytical, communication and documentation skills