Senior Layout Design Engineer — Lead Analog/CMOS Layout

The Preferred Supplier; Delft; On-site; EUR 70,000 - 90,000; Full time

Job summary

A leading technology firm in the Netherlands is seeking a Sr. Layout Design Engineer responsible for top-level chip planning and custom layouts for CMOS and BiCMOS circuits. The ideal candidate will have at least 10 years of experience in layout design, strong skills in Cadence Virtuoso, and a solid understanding of layout challenges including parasitics and signal integrity. The role demands attention to detail and collaborative skills in a fast-paced environment.

Qualifications

• 10 years of experience with layout design for analog and full-custom digital blocks.
• Conceptual understanding of layout topics such as parasitics, matching, and latch-up.
• Strong capability of solving device matching and electro-migration issues.

Responsibilities

• Lead top-level chip-planning and perform layout for CMOS and BiCMOS circuits.
• Verify layouts to pass DRC, LVS, and ERC checks.
• Perform floor-planning and power line planning tasks.

Skills

Layout design for analog and digital blocks

Cadence Virtuoso tools

Debugging DRC/LVS/ERC

Device matching

Signal integrity

Education

AA/AS Degree in Layout Design or related field

Tools

Cadence Virtuoso

Mentor Calibre

Job description

A leading technology firm in the Netherlands is seeking a Sr. Layout Design Engineer responsible for top-level chip planning and custom layouts for CMOS and BiCMOS circuits. The ideal candidate will have at least 10 years of experience in layout design, strong skills in Cadence Virtuoso, and a solid understanding of layout challenges including parasitics and signal integrity. The role demands attention to detail and collaborative skills in a fast-paced environment.