Sr Layout design engineer

The Preferred Supplier; Delft; On-site; EUR 70,000 - 90,000; Full time

Job summary

A leading technology firm in the Netherlands is seeking a Sr. Layout Design Engineer responsible for top-level chip planning and custom layouts for CMOS and BiCMOS circuits. The ideal candidate will have at least 10 years of experience in layout design, strong skills in Cadence Virtuoso, and a solid understanding of layout challenges including parasitics and signal integrity. The role demands attention to detail and collaborative skills in a fast-paced environment.

Qualifications

• 10 years of experience with layout design for analog and full-custom digital blocks.
• Conceptual understanding of layout topics such as parasitics, matching, and latch-up.
• Strong capability of solving device matching and electro-migration issues.

Responsibilities

• Lead top-level chip-planning and perform layout for CMOS and BiCMOS circuits.
• Verify layouts to pass DRC, LVS, and ERC checks.
• Perform floor-planning and power line planning tasks.

Skills

Layout design for analog and digital blocks

Cadence Virtuoso tools

Debugging DRC/LVS/ERC

Device matching

Signal integrity

Education

AA/AS Degree in Layout Design or related field

Tools

Cadence Virtuoso

Mentor Calibre

Job description

Our client, amarket leader in MEMS timing, offers MEMS-based silicon timing system solutions. Our client's configurable solutions offer a rich feature set that enables customers to differentiate their products with high performance, small size, low power, and high reliability. With over 2 billion devices shipped to date, they are changing the timing industry.

Job Summary

The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The Sr. Layout Design Engineer will review and coordinate work content performed by offshore physical layout designers.

Responsibilities

• Lead Top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits
• Perform schematic-driven layout and design constraints
• Design die-area efficient layouts according to circuit designer requirements
• Perform block or top-level layout designs
• Perform floor-planning, power line planning, shielding, and device-matching layout
• Verify layouts. Pass DRC, LVS, and ERC
• Contribute to various chip-level routing and layout needs
• Support other projects as needed by management

Qualifications & Requirements

• AA/AS Degree in Layout Design or related field or equivalent experience
• 10 years’ experience with layout design for analog and full-custom digital blocks
• Proficient in using layout editing tools in the Cadence Virtuoso design environment
• Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
• Conceptual understanding of layout topics such as parasitics, matching, crosstalk, transistorlayout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTNisolation
• Strong capability of solving device matching, electro-migration, signal integrity and powerdistribution problems while meeting area constraints
• Experience in chip‑level floor planning and analog block integration
• Ability to use productivity‑enhancing tools and design scripts to further automate tasks is also desirable

Desired Characteristics & Attributes

• Attention to detail, organized, accurate and can produce efficient layout techniques
• Has a good track record of on-time work delivery
• Has a self-motivated, team player with good communication skills
• Ability to work well with others in a fast-paced collaborative team environment