Analog Layout Engineer – 22nm CMOS & High-Speed SERDES

Chipright

Netherlands

On-site

EUR 70,000 - 100,000

Full time

14 days+

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Job summary

Chipright seeks highly motivated Analog Layout development engineer to work within a team of experienced engineers on 22 nanometer technology. The role requires 5+ years in Analog Layout, high-speed SERDES layout, and deep sub-micron CMOS expertise.

Proficiency withSynopsys and Cadence tools is essential, with strong architectural influence and robust debugging skills. You will engage in floor planning, power routing, ESD design, and comprehensive physical verification, collaborating with tool

Qualifications

5+ years’ minimum experience in Analog Layout.
Experience in High Speed Layout of SERDES.
Experience in Layout of blocks such as PLLs, Transceivers, Receivers.
Experience working on deep sub-micron CMOS (28nm or less).
Proficient with Synopsys & Cadence tools.
Ability to influence the architecture level and design to ensure layout is achievable.
Experience with Floor Planning, Power Routing and ESD level design.
Experience with Place & Route, Layout Finishing.
Experience with DRC and all aspects of Physical Verification.
Experience in working with EDA tool suppliers to yield best results.
Strong debug & problem-solving skills.
Educated to degree level with excellent analytical, communication and documentation skills.