Digital IC/RTL Senior Design Engineer

The Preferred Supplier; Delft; On-site; EUR 70,000 - 90,000; Full time

Job summary

A leading MEMS technology company is seeking a Digital IC/RTL Senior Design Engineer based in Delft. In this role, you will lead RTL design for next-generation MEMS products, focusing on high-performance and low-power solutions. The position requires a deep understanding of digital design, proficiency in EDA tools, and a strong educational background in Electrical Engineering, with at least 5 years of relevant experience in the industry. You will work collaboratively within a fast-paced environment to develop innovative solutions.

Qualifications

• 5 years of experience in Electrical Engineering.
• Extensive experience in digital block verification strategies.
• Track record in digital design from architecture to sign-off.

Responsibilities

• Develop and verify digital block architectures and RTL designs.
• Document specifications and perform RTL design verification.
• Collaborate with teams to optimize DFT and achieve production release.

Skills

Digital architecture development

Writing detailed block-level specifications

DSP functions

Verilog

VHDL

SystemVerilog

Signal processing algorithms

Problem-solving

Education

M.Sc. or Ph.D. in Electrical Engineering

Tools

EDA tools

Matlab

Simulink

Job description

About the job Digital IC/RTL Senior Design Engineer

About X

X Corporation(Nasdaq: X), a market leader in MEMS timing, offers MEMS-based silicon timing system solutions. X configurable solutionsoffer a rich feature set that enables customers to differentiate their products with high performance, small size,low power, and high reliability. With over2 billion devices shipped to date, X is changing the timing industry.

The ASIC Senior Design Engineer will leadand contribute to circuit design for next-generation products. These products have applications rangingfrom high-performance Networking and Communications Infrastructure to ultra-lowpower Mobile platforms including wearable devices.

Responsibilities:

• Development and verification of digital block architectures and RTL design for various functions including control state machine, IO controllers, digital signal processing (DSP), and multiple clock domain interface management
• Work with other digital ormixed-signal designers to define specifications for digital blocks and interfaces
• Analyze architecture, RTL design for optimal performance, area and power constraints trade- offs
• Document detailed block and top -level specifications
• Perform block level RTL design and verification using industry leading EDA tools
• Support backend design flow,including RTL synthesis, clock tree synthesis, scan and DFT insertion, place and route,and netlist verification
• Collaborate with analog designengineers, CAD, systems engineering, test engineering and applications teams to ensure defineoptimal DFT, DFM features and achieve rapid silicon bring- up and time to production release
• Participate in the bring-up of silicon prototypes
• Analyze circuit for failureroot cause analysis, investigate anomalous observations in silicon acrossvarious conditions, including PVTvariations, and propose solutions

Qualifications & Requirements:

• M.Sc. or Ph.D. with 5 years of experience in Electrical Engineering
• Proven track recordat each stage of the following:
• Digital architecture development and technical feasibility studies
• Writing detailed block-level specifications and review documents
• Detailed design and simulationof one or more of the following: digital state machines, DSP functions, IO controllers, multiple blockinterface management including multi-clock domain designs, microcontroller designand implementation, memory and register file controllers
• Proficiency with EDA tools and design languages including Verilog, VHDL, SystemVerilog
• Extensive experience in digitalblock verification strategies
• Understanding of digital designflow from architecture design to sign-off
• Experience with DSP concepts, circuits, architectures, and implementation
• Ability to communicate and workeffectively with geographically dispersed teams of mixed- signal,digital, layout, and verificationsengineers
• Ability to work independently and drive solutions to challenging problems
• Good understanding of modelingsignal processing algorithm using Matlab or Simulink
• Experience in performing synthesis, static timinganalysis, and netlistverifications
• Understanding of digital backendflow for Place & Route (PNR)
• Experience in digital DFT flow (stuck-at / TDF scan insertion and ATPG)

Desired Characteristics & Attributes:

• Passionate, self-starter with strong commitment to flawless execution
• Excellent written and verbalcommunication skills required
• Ability to work well with others in a fast-paced collaborative team environment