Test Design Engineer

CADFEM APAC; Penang; On-site; MYR 90,000 - 150,000; Full time

Job summary

CADFEM APAC is seeking a DFT Engineer to design and implement DFT architectures for SoC/ASIC projects in Penang. You will work on Scan insertion, MBIST/LBIST, ATPG, and test coverage analysis, ensuring robust DFT flows across pre- and post-silicon stages.

The role requires hands-on experience with DFT tooling and scripting, along with collaboration with verification and backend teams to meet quality standards and delivery timelines.

Qualifications

• Experience in DFT / VLSI design.
• Hands-on experience in SoC/ASIC DFT implementation.
• Exposure to full-chip or block-level DFT flows.
• Experience with advanced nodes is a plus.
• Exposure to silicon bring-up and post-silicon validation.

Responsibilities

• Design and implement DFT architectures, including Scan insertion, MBIST (Memory BIST) and LBIST (Logic BIST)
• Perform ATPG (Automatic Test Pattern Generation) and analyze test coverage
• Implement and optimize test compression techniques to improve efficiency
• Debug test failures during pre-silicon and post-silicon stages
• Support silicon bring-up and validation activities

Skills

DFT design

ATPG fault

Boundary scan

SoC/ASIC focus

Education

Electronics / Electrical / VLSI Engineering

Tools

Synopsys DFT Compiler

Scan architecture

ATPG

JTAG boundary scan

Job description

Key Responsibilities

• Design and implement DFT architectures, including Scan insertion, MBIST (Memory BIST) and LBIST (Logic BIST)
• Perform ATPG (Automatic Test Pattern Generation) and analyze test coverage
• Implement and optimize test compression techniques to improve efficiency
• Debug test failures during pre-silicon and post-silicon stages
• Support silicon bring-up and validation activities

Work closely with:

• Verification teams for DFT validation
• Physical Design (backend) teams for DFT implementation and closure
• Ensure compliance with DFT methodologies and quality standards
• Analyze and resolve coverage gaps and testability issues
• Support production test readiness and yield improvement

Education:

Electronics / Electrical / VLSI Engineering.

Experience:

• Experience in DFT / VLSI design.
• Hands-on experience in SoC/ASIC DFT implementation.
• Exposure to full-chip or block-level DFT flows.
• Experience with advanced nodes is a plus.
• Exposure to silicon bring-up and post- silicon validation

Technical Skills:

Strong experience with:

• Synopsys DFT Compiler
• Scan architecture and insertion
• ATPG and fault modeling
• Boundary scan (JTAG) implementation

Good understanding of:

• Timing and physical design constraints related to DFT
• Familiarity with scripting (Tcl/Python) is an added advantage