DFT Engineer for ASIC/SoC Test & Validation

Technopals Pte.; Penang; On-site; MYR 90,000 - 150,000; Full time

Job summary

Technopals Pte. Ltd. in Penang, Malaysia, seeks a Design for Test (DFT) Engineer with 4+ years of hands-on experience to implement and verify DFT architectures for complex ASIC/SoC. Strong background in Siemens Tessent and advanced ATPG/scan techniques is required.

The role involves performing scan insertion, ATPG pattern generation, coverage analysis, and documenting DFT methodologies for project reviews. Familiarity with PCIe/SoC test flows and scripting to automate tasks is a plus.

Qualifications

• 4+ years of hands-on experience in implementing and verifying DFT architectures for complex ASIC/SoC.

Responsibilities

• Perform scan insertion, ATPG pattern generation, and coverage analysis using industry tools.
• Document DFT methodologies, test coverage metrics, and deliverables for project reviews.
• Spyglass Check

Skills

Siemens Tessent

Scan

ATPG

Boundary Scan

JTAG

Fault Simulation

Coverage Analysis

Low-Power Test

Education

B.E./B.Tech./M.E./M.Tech in Electronics or VLSI

Tools

Script: Perl/Tcl/Python

Job description

Technopals Pte. Ltd. in Penang, Malaysia, seeks a Design for Test (DFT) Engineer with 4+ years of hands-on experience to implement and verify DFT architectures for complex ASIC/SoC. Strong background in Siemens Tessent and advanced ATPG/scan techniques is required.

The role involves performing scan insertion, ATPG pattern generation, coverage analysis, and documenting DFT methodologies for project reviews. Familiarity with PCIe/SoC test flows and scripting to automate tasks is a plus.