Technical Staff Engineer - Design

SHIVZ Solution; Penang; On-site; MYR 240,000 - 360,000; Full time

Job summary

SHIVZ Solution is seeking an experienced ASIC IC Design Lead to drive technically in the ASIC design implementation domain, from architectural understanding to timing signoff for tapeout.

You will lead RTL2GDS implementation and flow improvements, mentor technical teams, and advance design methodologies for 7nm and below processes while delivering robust signoffs.

Qualifications

• Bachelor’s/Master’s Degree in Electrical/Electronics Engineering, with 8-12 years of ASIC I.C. Design working experience.
• Cadence Genus or Synopsys DesignCompiler expertise.
• Cadence Tempus or Synopsys Primetime expertise.
• Exposure to 7nm and below advanced process nodes.
• Familiar with System-Verilog foundation and coding.
• Strong scripting skills in Perl, TCL, Shell or Python.

Responsibilities

• Lead ASIC design implementation, from architectural understanding to timing signoff for tapeout.
• Develop RTL2GDS implementation and flow improvements.
• Derive timing constraints from design specs and secure signoff.
• DFT implementation, covering scan insertion and related techniques.
• Low power design optimization from architectural feedback to layout.
• Provide technical guidance and review for team members.
• Create technical IP such as patents and trade secrets.
• Document design implementation procedures using corporate templates.
• Complete audit and checklist fill-in per Design Control Procedures (DCP).
• Collaborate with project manager, product development and ATPG teams; manage CAD/TA flow.

Skills

ASIC design

RTL design

Timing signoff

DFT

Low power design

Scripting (Perl/TCL/Python)

Leadership

Problem solving

Education

Bachelor’s/Master’s Degree in Electrical/Electronics Engineering

Tools

Cadence Genus

Synopsys DesignCompiler

Cadence Tempus

Synopsys PrimeTime

Job description

• To lead technically in ASIC design implementation domain, which may include stages from design architectural understanding till timing signoff for tapeout
• To develop and signoff I.C. design projects RTL2GDS implementation and flow improvement.

Responsibilities

• Architectural and micro-architectural intent understanding
• RTL design structure for effective and efficient synthesis implementation
• Derive timing constraints from design spec, review and validate with respective designer/architect for signoff
• Design-For-Test (DFT) implementation, covering basic scan insertion, compression, LOC/LOS, RAMBIST all the way to advanced handling for performance/schedule/coverage trade-off
• Low power design; starting from architectural feedback, vector-driven synthesis/layout optimization and leakage/dynamic power control techniques
• Provide technical guidance and review for team members in solving complex challenges, with high problem-solving skill and critical thinking capability
• Creating technical intellectual property such as patents and trade secrets
• Drive for Best-in-Class design implementation approach/process or new design methodologies benchmarking o To document I.C. Design implementation and work procedures
• Capturing design implementation approach, consideration, challenges and solutions employed using corporate template documentation
• Complete audit and checklist fill-in, review and closure in compliance to corporate Design Control Procedures (DCP)
• Filing issues, solution details and review confirmation in project ticketing system (PEPS) or CAD ticketing system (JIRA)
• Project manager, product-development and ATPG team on project related issues
• CAD/TA on flow methodology

Qualifications

• Bachelor’s/Master’s Degree in Electrical/Electronics Engineering, with 8-12 years of ASIC I.C. Design working experience
• Cadence Genus or Synopsys DesignCompiler expertise
• Cadence Tempus or Synopsys Primetime expertise
• Exposure to 7nm and below advanced process nodes
• Familiar with System-Verilog foundation and coding
• Strong scripting skills in Perl, TCL, Shell or Python