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Technopals Pte. Ltd. in Penang, Malaysia, seeks a Design for Test (DFT) Engineer with 4+ years of hands-on experience to implement and verify DFT architectures for complex ASIC/SoC. Strong background in Siemens Tessent and advanced ATPG/scan techniques is required.
The role involves performing scan insertion, ATPG pattern generation, coverage analysis, and documenting DFT methodologies for project reviews. Familiarity with PCIe/SoC test flows and scripting to automate tasks is a plus.
Job Description :
Role Overview: We are looking for a Design for Test(DFT) Engineer to join our growing team in Malaysia. The ideal candidate shouldhave 4+ years of hands-on experience in implementing and verifying DFTarchitectures for complex ASIC/SoC
Key Responsibilities:
Technical Skills Required:
Soft Skills :
Education Qualification :B.E / B.Tech / M.E / M.Tech in Electronics, Electrical, or VLSI Engineering.
Technopals Pte.Ltd. is an Equal Opportunity Employer and does not discriminate on the basis of race or ethnicity, religion, sex, national origin, age, veteran disability or genetic information or any other reason prohibited by law in employment.