Physical Design (CAD) Engineer

UST; Penang; On-site; MYR 120,000 - 200,000; Full time

Job summary

UST in Penang, Malaysia seeks an experienced Physical Design CAD Flow Engineer to develop, automate, and maintain advanced ASIC flows. The role focuses on Fusion Compiler, PrimeTime, Formality, and Calibre/ICV for signoff and verification.

You will automate flows with Tcl/Python, collaborate across PD, STA, verification, and methodology teams, and drive productivity and tapeout readiness across projects.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
• Strong ASIC Physical Design and/or CAD methodology background.
• Hands-on experience with Fusion Compiler (FC), PrimeTime (PT), Formality.
• Scripting in Tcl and Python; Perl/Shell experience is beneficial.

Responsibilities

• Develop, integrate, and maintain Physical Design CAD flows from implementation through signoff.
• Support and optimize Fusion Compiler flows including synthesis, floorplanning, placement, CTS, routing, and optimization.
• Develop and maintain PrimeTime STA/signoff flows, including timing analysis and debugging.
• Support Formality flows for RTL-to-gate and gate-to-gate formal equivalence checking.
• Develop and maintain physical verification flows using Calibre and/or ICV, including DRC/LVS-related checks.
• Automate design flows, reporting, regression, and quality checks using Tcl, Python, Perl and/or shell scripting.
• Debug EDA tool and flow issues and work closely with PD engineers to improve PPA, turnaround time, flow robustness, and productivity.
• Integrate new EDA tool versions and methodologies into production design environments.
• Collaborate with design, STA, verification, and methodology teams to support project tapeout requirements.

Skills

Physical Design knowledge

CAD methodology

Scripting (Tcl/Python)

Linux-based EDA

Problem solving

Education

Electrical Engineering, Computer Engineering, or Computer Science

Tools

Fusion Compiler (FC)

PrimeTime (PT)

Formality

Calibre/ICV

Tcl

Python

Job description

We are looking for an experienced Physical Design CAD Flow Engineer to develop, automate, maintain, and support advanced ASIC physical design and signoff flows. The ideal candidate will have strong expertise in Synopsys Fusion Compiler, PrimeTime, Formality, and physical verification using Siemens Calibre and/or Synopsys ICV.

Key Responsibilities

• Develop, integrate, and maintain Physical Design CAD flows from implementation through signoff.
• Support and optimize Fusion Compiler (FC) flows including synthesis, floorplanning, placement, CTS, routing, and optimization.
• Develop and maintain PrimeTime (PT) STA/signoff flows, including timing analysis and debugging.
• Support Formality flows for RTL-to-gate and gate-to-gate formal equivalence checking.
• Develop and maintain physical verification flows using Calibre and/or ICV, including DRC/LVS-related checks.
• Automate design flows, reporting, regression, and quality checks using Tcl, Python, Perl and/or shell scripting.
• Debug EDA tool and flow issues and work closely with Physical Design engineers to improve PPA, turnaround time, flow robustness, and productivity.
• Integrate new EDA tool versions and methodologies into production design environments.
• Collaborate with design, STA, verification, and methodology teams to support project tapeout requirements.

Required Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• Strong ASIC Physical Design and/or CAD methodology background.
• Hands-on experience with:
• Synopsys Fusion Compiler (FC)
• Synopsys PrimeTime (PT)
• Synopsys Formality
• Siemens Calibre and/or Synopsys ICV
• Strong scripting skills in Tcl and Python; Perl/Shell experience is beneficial.
• Good understanding of the ASIC implementation flow, including synthesis, P&R, STA, formal equivalence, and physical verification.
• Strong debugging and problem-solving skills in Linux-based EDA environments.

Preferred Qualifications

• Experience developing reusable, automated CAD flows for multiple projects or technology nodes.
• Experience with advanced-node ASIC/SOC implementation and signoff.
• Familiarity with UPF/low-power flows, MMMC, ECO, timing closure, and hierarchical design methodologies.
• Experience working with foundry PDKs and integrating technology-specific collateral into production flows.

Key skills: Physical Design CAD, CAD Flow, EDA Methodology, Fusion Compiler, FC, PrimeTime, PT, Formality, Calibre, ICV, STA, P&R, Physical Verification, Tcl, Python.