Lead ASIC Design Engineer — RTL to Tapeout

Microchip Technology Inc.; Penang; On-site; MYR 180,000 - 260,000; Full time

Job summary

Microchip Technology Inc. in Penang, Malaysia seeks a senior ASIC design leader to drive implementation from architecture to tapeout timing signoff, leveraging extensive CAD flows.

You will oversee RTL2GDS implementation and flow improvements, with a focus on DFT, low-power techniques, and cross-functional collaboration. The ideal candidate has 12–16 years of ASIC IC design experience and hands-on expertise with Cadence Genus, DesignCompiler, Tempus, and PrimeTime to deliver high-quality,

Qualifications

• Bachelor’s/Master’s Degree in Electrical/Electronics Engineering with 12–16 years of ASIC IC Design experience.
• Cadence Genus or Synopsys DesignCompiler expertise.
• Cadence Tempus or Synopsys Primetime expertise.

Responsibilities

• Lead technically in ASIC design implementation from architecture through timing signoff for tapeout.
• Develop and signoff RTL2GDS flow and improve design flows.

Education

Bachelor’s/Master’s Degree in Electrical/Electronics Engineering

Tools

Cadence Genus

Synopsys DesignCompiler

Cadence Tempus

Synopsys Primetime

Job description

Microchip Technology Inc. in Penang, Malaysia seeks a senior ASIC design leader to drive implementation from architecture to tapeout timing signoff, leveraging extensive CAD flows.

You will oversee RTL2GDS implementation and flow improvements, with a focus on DFT, low-power techniques, and cross-functional collaboration. The ideal candidate has 12–16 years of ASIC IC design experience and hands-on expertise with Cadence Genus, DesignCompiler, Tempus, and PrimeTime to deliver high-quality,