Principal Engineer – Design

FHLB Des Moines; Penang; On-site; MYR 180,000 - 280,000; Full time

Job summary

FHLB Des Moines is seeking an experienced ASIC design lead in Penang to drive from RTL to GDS implementation and tapeout readiness. You will work on timing signoffs, DFT, and low-power optimization while guiding team members through complex challenges.

The ideal candidate has 12–16 years of ASIC IC design experience, proficiency with Cadence and Synopsys tools, SystemVerilog, and scripting skills across Perl/TCL/Shell/Python. Travel up to 25% may be required.

Qualifications

• Bachelor’s or Master’s Degree in Electrical/Electronics Engineering.
• Expertise in Cadence Genus or Synopsys DesignCompiler.
• Expertise in Cadence Tempus or Synopsys PrimeTime.
• Exposure to 7nm and below process nodes.
• Familiarity with System-Verilog.
• Strong scripting in Perl, TCL, Shell or Python.
• Travel 0% – 25%.

Responsibilities

• Lead technically in ASIC design implementation from RTL to GDS for tapeout readiness.
• Derive timing constraints and obtain signoff with designers.
• Implement DFT, including scan insertion and related techniques.
• Optimize low-power design through architectural feedback and layout/synthesis improvements.
• Provide guidance and review for team members on complex design challenges.

Skills

SystemVerilog knowledge

Scripting skills

ASIC IC design

Education

Bachelor's or Master's in Electrical/Electronics Engineering

Tools

Cadence Genus

Synopsys DesignCompiler

Cadence Tempus

Synopsys PrimeTime

Job description

Job Description: To lead technically in ASIC design implementation domain, which may include stages from design architectural understanding to timing signoff for tapeout and to develop and signoff I.C. design projects from RTL to GDS implementation and flow improvement.

Responsibilities

• Architectural and micro-architectural intent understanding of RTL design structure for effective and efficient synthesis implementation.
• Derive timing constraints from design specifications, review and validate with respective designer/architect for signoff.
• Design‑For‑Test (DFT) implementation, covering basic scan insertion, compression, LOC/LOS, RAMBIST through advanced handling for performance/schedule/coverage trade‑off.
• Low‑power design: starting from architectural feedback, vector‑driven synthesis/layout optimization and leakage/dynamic power control techniques.
• Provide technical guidance and review for team members in solving complex challenges, with high problem‑solving skill and critical thinking capability.
• Create technical intellectual property such as patents and trade secrets.
• Drive best‑in‑class design implementation approach/process or new design methodologies benchmarking.
• Document I.C. design implementation and work procedures, capturing design implementation approach, considerations, challenges and solutions employed using corporate template documentation.
• Complete audit and checklist fill‑in, review and closure in compliance with corporate Design Control Procedures (DCP).
• File issues, solution details and review confirmation in project ticketing system (PEPS) or CAD ticketing system (JIRA).
• Interface with Project Manager, product‑development and ATPG team on project‑related issues, CAD/TA on flow methodology.

Requirements / Qualifications

• Bachelor’s or Master’s Degree in Electrical/Electronics Engineering, with 12‑16 years of ASIC I.C. design working experience.
• Expertise in Cadence Genus or Synopsys DesignCompiler.
• Expertise in Cadence Tempus or Synopsys PrimeTime.
• Added advantage: Exposure to 7nm and below advanced process nodes.
• Familiarity with System‑Verilog foundation and coding.
• Strong scripting skills in Perl, TCL, Shell or Python.
• Travel requirement: 0% – 25%.