Principal Engineer – Design

Microchip Technology Inc.; Penang; On-site; MYR 180,000 - 260,000; Full time

Job summary

Microchip Technology Inc. in Penang, Malaysia seeks a senior ASIC design leader to drive implementation from architecture to tapeout timing signoff, leveraging extensive CAD flows.

You will oversee RTL2GDS implementation and flow improvements, with a focus on DFT, low-power techniques, and cross-functional collaboration. The ideal candidate has 12–16 years of ASIC IC design experience and hands-on expertise with Cadence Genus, DesignCompiler, Tempus, and PrimeTime to deliver high-quality,

Qualifications

• Bachelor’s/Master’s Degree in Electrical/Electronics Engineering with 12–16 years of ASIC IC Design experience.
• Cadence Genus or Synopsys DesignCompiler expertise.
• Cadence Tempus or Synopsys Primetime expertise.

Responsibilities

• Lead technically in ASIC design implementation from architecture through timing signoff for tapeout.
• Develop and signoff RTL2GDS flow and improve design flows.

Education

Bachelor’s/Master’s Degree in Electrical/Electronics Engineering

Tools

Cadence Genus

Synopsys DesignCompiler

Cadence Tempus

Synopsys Primetime

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description

• To lead technically in ASIC design implementation domain, which may include stages from design architectural understanding till timing signoff for tapeout
• To develop and signoff I.C. design projects RTL2GDS implementation and flow improvement.

Responsibilities Include (as Applicable)

• Architectural and micro-architectural intent understanding
• RTL design structure for effective and efficient synthesis implementation
• Derive timing constraints from design spec, review and validate with respective designer/architect for signoff
• Design-For-Test (DFT) implementation, covering basic scan insertion, compression, LOC/LOS, RAMBIST all the way to advanced handling for performance/schedule/coverage trade-off
• Low power design; starting from architectural feedback, vector-driven synthesis/layout optimization and leakage/dynamic power control techniques
• Provide technical guidance and review for team members in solving complex challenges, with high problem-solving skill and critical thinking capability
• Creating technical intellectual property such as patents and trade secrets
• Drive for Best-in-Class design implementation approach/process or new design methodologies benchmarking

To document I.C. Design implementation and work procedures

• Capturing design implementation approach, consideration, challenges and solutions employed using corporate template documentation
• Complete audit and checklist fill-in, review and closure in compliance to corporate Design Control Procedures (DCP)
• Filing issues, solution details and review confirmation in project ticketing system (PEPS) or CAD ticketing system (JIRA)

To interface with

• Project manager, product-development and ATPG team on project related issues
• CAD/TA on flow methodology

Requirements/Qualifications

• Bachelor’s/Master’s Degree in Electrical/Electronics Engineering, with 12-16 years of ASIC I.C. Design working experience
• Cadence Genus or Synopsys DesignCompiler expertise
• Cadence Tempus or Synopsys Primetime expertise

Added advantage

• Exposure to 7nm and below advanced process nodes
• Familiar with System-Verilog foundation and coding
• Strong scripting skills in Perl, TCL, Shell or Python

Travel Time

0% - 25%