SoC Physical Design Engineer: Power, Timing & Signoff

Altera; Bayan Lepas; On-site; MYR 134,000 - 201,000; Full time

Job summary

Altera in Penang, Malaysia seeks a seasoned Physical Design Engineer to drive complete back-end flows from RTL through GDS for manufacturing. You will handle synthesis, place-and-route, timing closure, clock tree synthesis, and signoff verification with a focus on power, performance, and area.

The role requires 3+ years in physical design, experience with deep submicron nodes, and scripting in Perl/TCL/Python, plus VHDL/Verilog knowledge.

Qualifications

• 3+ years of relevant experience in physical design.
• Tape-out experience in deep submicron process nodes.
• Deep knowledge of physical design flow and EDA tools.
• Hands-on experience with STA/LEC flows and DRC/ERC signoff.
• Proficiency with VHDL/Verilog and scripting languages (Perl/TCL/Python).
• Experience mentoring junior team members and working in diverse teams.

Responsibilities

• Performs physical design implementation from RTL to GDS for manufacturing.
• Executes synthesis, place and route, clock tree synthesis, floor planning, STA, PNR, and power integrity analyses.
• Performs design verification and signoff, including formal equivalence, reliability checks, and layout verification.
• Analyzes results and recommends fixes for current and future architectures.
• Applies expertise in clock design, timing closure, power management, and DFT using standard EDA tools.
• Contributes to design methodology development and flow automation.

Skills

Analytical thinking

Teamwork

Multitasking

Mentoring juniors

Initiative

Education

Bachelor's degree in Computer or Electronic Engineering

Tools

VHDL

Verilog

Perl/TCL/Python

EDA tools

Job description

Altera in Penang, Malaysia seeks a seasoned Physical Design Engineer to drive complete back-end flows from RTL through GDS for manufacturing. You will handle synthesis, place-and-route, timing closure, clock tree synthesis, and signoff verification with a focus on power, performance, and area.

The role requires 3+ years in physical design, experience with deep submicron nodes, and scripting in Perl/TCL/Python, plus VHDL/Verilog knowledge.