Senior Physical Design Engineer

Altera; Penang; On-site; MYR 180,000 - 300,000; Full time

Job summary

Altera in Penang, Malaysia, seeks a Senior Physical Design Engineer to drive the full physical design flow from RTL to GDSII and to ensure manufacturability. You will handle synthesis, place-and-route, STA, clock tree synthesis, floorplanning, and sign-off while optimizing power, frequency, and die area.

You will mentor junior engineers, contribute to method development, and work across multiple clock domains in a collaborative, global environment.

Qualifications

• Bachelor’s degree in computer engineering, electronic engineering or related field.
• 5+ years of relevant experience in physical design and tape-out in deep submicron processes.
• Extensive knowledge of physical design flow and signoff (STA, LEC, ERC, DRC).
• Hands-on scripting in Perl, TCL, Python; HDL knowledge (VHDL/Verilog).
• Experience mentoring junior team members and working in diverse teams.

Responsibilities

• Perform physical design implementation from RTL to GDS to create a manufacturable design database.
• Contribute to synthesis, place-and-route, clock tree synthesis, floorplanning, STA, and power integrity analyses.
• Execute verification and signoff flows (formality, STA, ERC, DRC) and fix violations.
• Analyze results, optimize power, performance, and area; improve design methodologies and flow automation.

Skills

Verilog

VHDL

Python

Perl

TCL

Mentoring

Problem solving

Teamwork

Education

Bachelor's degree in Computer Engineering or Electronic Engineering

Master's degree in related field

Tools

EDA tools

Job description

## Senior Physical Design EngineerApplylocations: Penang 15, Penang, Malaysiatime type: Full timeposted on: Posted Todayjob requisition id: R02751# **Job Details:**### ## **Job Description:**Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.Analyzes results and makes recommendations to fix violations for current and future product architecture.Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.Optimizes design to improve product-level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.### ## **Qualifications:****Education Requirements:** Bachelor's degree in computer engineering, electronic Engineering or related field.**Minimum Qualifications**5+ years of relevant experience in the following areas:* Have multiple tape-out experience in deep submicron process nodes* in depth, extensive knowledge and hands-on experience in physical design flow and relevant EDA tools* in depth, extensive knowledge and hands-on experience in physical design signoff flow, such as STA flow, LEC flow, ERC flow and DRC flow.* Hands-on expertise with scripting languages such as Perl, TCL, Python and knowledge of hardware description languages of VHDL and Verilog.* Experience of mentoring junior team members and charting their development for success.* Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.**Preferred Requirements:*** Bachelor or master's degree in computer engineering, Electronic Engineering or related field.* 5+ years of experience in the following areas: + Physical design involving multiple clock domains and clock, power management. + Low power design, tools and methodologies. Power intent UPF specifications.### ## **Job Type:**Regular### ## **Shift:**Shift 1 (Malaysia)### ## **Primary Location:**Penang 15, Penang, Malaysia### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.**About Altera**Altera: Accelerating InnovatorsAltera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.