Physical Design Engineer: Full-Chip PnR & STA Expert

UST Malaysia; Bayan Lepas; On-site; MYR 90,000 - 130,000; Full time

Job summary

UST Malaysia in Bayan Lepas, Penang, invites an experienced ASIC physical design engineer to drive full-chip physical implementation, including floorplanning, placement, CTS, routing and optimization, with a focus on timing closure.

You will collaborate with front-end, STA and power teams to resolve timing, congestion and design-rule issues, develop methodology scripts (Tcl, Perl or Python), and use ICC2/Fusion Compiler or Cadence Innovus for implementation and signoff.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field.
• At least 3–8 years of ASIC physical design experience (PnR and STA focus).
• Strong hands-on experience with FinFET and advanced nodes (16nm, 14nm, 12nm, sub-10nm).
• Proficiency in timing analysis, optimization, and closure using PrimeTime or equivalent.
• Experience in PNR implementation flows using ICC2/Fusion Compiler, or Cadence Innovus.
• Solid understanding of design constraints (SDC), RC extraction, and timing ECOs.
• Scripting in Tcl, Perl, Python.
• Willing to work in Bayan Lepas, Penang Malaysia.

Responsibilities

• Drive full-chip physical implementation including floorplanning, placement, CTS, routing, and optimization.
• Perform timing closure across MCMM to meet PPA goals.
• Conduct STA signoff validation and timing ECOs.
• Perform physical verification (DRC/LVS) and crosstalk analysis.
• Collaborate with frontend, STA, and power teams to resolve issues.
• Develop automation scripts to streamline PD and STA workflows.
• Utilize PnR tools (ICC2, Fusion Compiler, Innovus) for implementation and optimization.
• Support tape-out activities and maintain physical database.

Skills

Timing analysis

Static timing analysis (STA)

PNR flows

Scripting (Tcl, Perl, Python)

Physical design (PnR)

Floorplanning/Placement/CTS/Routing

FinFET/advanced nodes

Reliability/Signoff

Education

Bachelor’s or Master’s degree in Electrical/Electronic Engineering

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

PrimeTime

Calibre

Job description

UST Malaysia in Bayan Lepas, Penang, invites an experienced ASIC physical design engineer to drive full-chip physical implementation, including floorplanning, placement, CTS, routing and optimization, with a focus on timing closure.

You will collaborate with front-end, STA and power teams to resolve timing, congestion and design-rule issues, develop methodology scripts (Tcl, Perl or Python), and use ICC2/Fusion Compiler or Cadence Innovus for implementation and signoff.