SoC DFX DV Engineer - Emulation & Debug Expert

UST; Penang; On-site; MYR 90,000 - 130,000; Full time

Job summary

UST is seeking a DFX Design Verification Engineer in Penang to execute and debug SoC-level DFX workloads on Palladium/Zebu/Veloce emulation platforms. You will validate JTAG, Boundary Scan, and DFX features while enabling software-driven validation and regression execution.

Collaboration with DV teams and SoC integration is expected. The role emphasizes strong SystemVerilog/UVM skills, RTL debugging, and proficiency in Python/TCL/Shell for automation, aligning with pre-silicon validation

Qualifications

• 4+ years of experience in Design Verification, DFX Verification, Emulation, or SoC Validation.
• Strong experience with Palladium, Zebu, or Veloce emulation platforms.
• Strong SystemVerilog and UVM knowledge.

Responsibilities

• Execute and debug SoC-level DFX verification workloads on emulation platforms.
• Validate JTAG, TAP controllers, Boundary Scan, debug infrastructure, test access mechanisms, and DFX-related SoC features.
• Enable DFX verification content, firmware, and software-driven validation in emulation environments.
• Support emulator build, compilation, partitioning, bring-up, and regression execution.
• Perform RTL debug, waveform analysis, and root-cause analysis of failing test scenarios.
• Validate DFX interactions with reset, clocking, power management, and subsystem integration flows.
• Execute large-scale SoC emulation regressions and drive bug closure.
• Develop regression automation, debug scripts, and reporting infrastructure using Python/TCL/Shell.
• Collaborate closely with DFX architects, RTL designers, DV teams, and SoC integration teams.

Skills

DFX Verification

Emulation Platforms

SystemVerilog

UVM

RTL Debugging

Python Scripting

TCL/Shell Scripting

JTAG/IEEE 1149.x

Boundary Scan

Debug Architectures

SoC Integration

Tools

Palladium

Zebu

Veloce

Job description

UST is seeking a DFX Design Verification Engineer in Penang to execute and debug SoC-level DFX workloads on Palladium/Zebu/Veloce emulation platforms. You will validate JTAG, Boundary Scan, and DFX features while enabling software-driven validation and regression execution.

Collaboration with DV teams and SoC integration is expected. The role emphasizes strong SystemVerilog/UVM skills, RTL debugging, and proficiency in Python/TCL/Shell for automation, aligning with pre-silicon validation