DFX DV Emulation Engineer (SoC Level)

UST; Penang; On-site; MYR 70,000 - 110,000; Full time

Job summary

UST in Penang, Malaysia is seeking a DFX Design Verification Engineer to execute and debug SoC-level DFX test suites on hardware emulation platforms such as Palladium, Zebu, or Veloce. You will validate DFX architecture, debug features, TAMs, and verify SoC integration in emulation environments.

Responsibilities include RTL debugging, waveform analysis, and regression development using Python/TCL/Shell. The role collaborates with DV teams and RTL designers to accelerate pre-silicon validation

Qualifications

• 4+ years of experience in Design Verification, DFX Verification, Emulation or SoC Validation.
• Experience with palladium, zebu, or veloce emulation platforms is required.
• Strong SystemVerilog and UVM knowledge.
• Familiarity with JTAG/IEEE 1149.x, Boundary Scan and TAM.

Responsibilities

• Execute and debug SoC-level DFX verification workloads on emulation platforms.
• Validate DFX features, test access mechanisms and debug infrastructure.
• Enable firmware/software-driven validation in emulation environments.
• Support emulator build, bring-up, and regression execution.
• Perform RTL debugging, waveform analysis, and root-cause analyses.
• Validate DFX interactions with clocking, reset, and power management flows.
• Drive large-scale emulation regressions and bug closure.
• Develop regression automation and reporting scripts using Python/TCL/Shell.
• Collaborate with DFX architects, RTL designers, DV teams, and integration teams.

Skills

Design Verification

DFX Verification

Emulation

SoC Validation

SystemVerilog

UVM

Palladium

Zebu

Veloce

Verdi

JTAG/IEEE 1149.x

Boundary Scan

Test Access Mechanisms (TAM)

Python scripting

TCL scripting

Shell scripting

Tools

Palladium

Zebu

Veloce

Verdi

Job description

We are seeking a DFX Design Verification Engineer with experience executing and debugging SoC-level DFX verification test suites on hardware emulation platforms such as Synopsys Zebu, Cadence Palladium, or Siemens Veloce. The role focuses on validating DFX architectures, debug features, test access mechanisms, and SoC-level verification scenarios in emulation environments to accelerate pre-silicon validation and signoff.

Key Responsibilities

• Execute and debug SoC-level DFX verification workloads on emulation platforms.
• Validate JTAG, TAP controllers, Boundary Scan, debug infrastructure, test access mechanisms, and DFX-related SoC features.
• Enable DFX verification content, firmware, and software-driven validation in emulation environments.
• Support emulator build, compilation, partitioning, bring-up, and regression execution.
• Perform RTL debug, waveform analysis, and root-cause analysis of failing test scenarios.
• Validate DFX interactions with reset, clocking, power management, and subsystem integration flows.
• Execute large-scale SoC emulation regressions and drive bug closure.
• Develop regression automation, debug scripts, and reporting infrastructure using Python/TCL/Shell.
• Collaborate closely with DFX architects, RTL designers, DV teams, and SoC integration teams.

Required Skills

• 4+ years of experience in Design Verification, DFX Verification, Emulation, or SoC Validation.
• Strong experience with Palladium, Zebu, or Veloce emulation platforms.
• Strong SystemVerilog and UVM knowledge.
• Experience with:
• JTAG / IEEE 1149.x
• Boundary Scan
• Debug and Trace Architectures
• Test Access Mechanisms (TAM)
• SoC DFX Integration
• Strong RTL debugging skills using Verdi or equivalent debug tools.
• Experience analyzing emulator regressions and waveform debug.
• Proficiency in Python, TCL, Perl, or Shell scripting.

Preferred Skills

• SoC-level verification experience involving CPU, GPU, AI, Networking, or Server SoCs.
• Knowledge of AXI, AHB, APB, PCIe, DDR, NoC, and subsystem integration.
• Experience with firmware-driven or software-based validation in emulation.
• Familiarity with power-aware verification and low-power debug scenarios