Design Verification Emulation Engineer

UST; Penang; On-site; MYR 90,000 - 180,000; Full time

Job summary

UST Malaysia is seeking an experienced Design Verification Engineer with a solid background in ASIC/SoC verification and hands-on exposure to FPGA and hardware emulation.

The candidate should be comfortable working across hardware and software environments, developing and debugging C-based tests for verification, and contributing to verification plans and system-level testing across FPGA prototypes and emulation platforms.

Qualifications

• Solid hands-on experience in Design Verification.
• Strong knowledge of SystemVerilog and UVM.
• Experience with functional and code coverage, assertions and debugging.
• Familiarity with FPGA-based verification/prototyping and/or hardware emulation.
• Good hands-on C programming ability.
• Understanding of ASIC/SoC architecture and HW/SW interaction.
• Experience with protocols such as AXI, AHB, APB, PCIe or similar is preferred.
• Experience with common verification tools from Cadence, Synopsys or Siemens EDA is advantageous.

Responsibilities

• Develop and execute verification plans for complex ASIC/SoC designs.
• Develop and maintain verification environments using SystemVerilog/UVM.
• Perform functional verification, debugging, regression testing and coverage closure.
• Work with FPGA prototypes and/or hardware emulation platforms for system-level verification.
• Develop and debug C/C++ based test cases for hardware/software verification.
• Debug RTL, testbench and HW/SW integration issues.
• Collaborate with design, verification, firmware and software teams to identify and resolve issues.
• Support bring-up and debugging of verification environments on FPGA/Emulation platforms.

Skills

Design Verification

SystemVerilog

UVM

C programming

C/C++

FPGA verification

Hardware emulation

ASIC/SoC

Debugging

Test development

AXI/PCIe

Cadence/Synopsys/Siemens EDA

Tools

Cadence

Synopsys

Siemens EDA

Job description

UST Malaysia is looking for an experienced Design Verification Engineer with a solid background in ASIC/SoC verification and hands-on exposure to FPGA and/or hardware emulation.

The candidate should be comfortable working across hardware and software environments, particularly developing and debugging C-based tests for verification.

Key Responsibilities

• Develop and execute verification plans for complex ASIC/SoC designs.
• Develop and maintain verification environments using SystemVerilog/UVM.
• Perform functional verification, debugging, regression testing and coverage closure.
• Work with FPGA prototypes and/or hardware emulation platforms for system-level verification.
• Develop and debug C/C++ based test cases for hardware/software verification.
• Debug RTL, testbench and HW/SW integration issues.
• Collaborate with design, verification, firmware and software teams to identify and resolve issues.
• Support bring-up and debugging of verification environments on FPGA/Emulation platforms.

Required Skills

• Solid hands-on experience in Design Verification.
• Strong knowledge of SystemVerilog and UVM.
• Experience with functional and code coverage, assertions and debugging.
• Familiarity with FPGA-based verification/prototyping and/or hardware emulation.
• Good hands-on C programming ability.
• Understanding of ASIC/SoC architecture and HW/SW interaction.
• Experience with protocols such as AXI, AHB, APB, PCIe or similar is preferred.
• Experience with common verification tools from Cadence, Synopsys or Siemens EDA is advantageous.