DFX Design Verification Engineer

UST; Penang; On-site; MYR 90,000 - 130,000; Full time

Job summary

UST is seeking a DFX Design Verification Engineer in Penang to execute and debug SoC-level DFX workloads on Palladium/Zebu/Veloce emulation platforms. You will validate JTAG, Boundary Scan, and DFX features while enabling software-driven validation and regression execution.

Collaboration with DV teams and SoC integration is expected. The role emphasizes strong SystemVerilog/UVM skills, RTL debugging, and proficiency in Python/TCL/Shell for automation, aligning with pre-silicon validation

Qualifications

• 4+ years of experience in Design Verification, DFX Verification, Emulation, or SoC Validation.
• Strong experience with Palladium, Zebu, or Veloce emulation platforms.
• Strong SystemVerilog and UVM knowledge.

Responsibilities

• Execute and debug SoC-level DFX verification workloads on emulation platforms.
• Validate JTAG, TAP controllers, Boundary Scan, debug infrastructure, test access mechanisms, and DFX-related SoC features.
• Enable DFX verification content, firmware, and software-driven validation in emulation environments.
• Support emulator build, compilation, partitioning, bring-up, and regression execution.
• Perform RTL debug, waveform analysis, and root-cause analysis of failing test scenarios.
• Validate DFX interactions with reset, clocking, power management, and subsystem integration flows.
• Execute large-scale SoC emulation regressions and drive bug closure.
• Develop regression automation, debug scripts, and reporting infrastructure using Python/TCL/Shell.
• Collaborate closely with DFX architects, RTL designers, DV teams, and SoC integration teams.

Skills

DFX Verification

Emulation Platforms

SystemVerilog

UVM

RTL Debugging

Python Scripting

TCL/Shell Scripting

JTAG/IEEE 1149.x

Boundary Scan

Debug Architectures

SoC Integration

Tools

Palladium

Zebu

Veloce

Job description

We are seeking a DFX Design Verification Engineer with experience executing and debugging SoC-level DFX verification test suites on hardware emulation platforms such as Synopsys Zebu, Cadence Palladium, or Siemens Veloce. The role focuses on validating DFX architectures, debug features, test access mechanisms, and SoC-level verification scenarios in emulation environments to accelerate pre-silicon validation and signoff.

Key Responsibilities

• Execute and debug SoC-level DFX verification workloads on emulation platforms.
• Validate JTAG, TAP controllers, Boundary Scan, debug infrastructure, test access mechanisms, and DFX-related SoC features.
• Enable DFX verification content, firmware, and software-driven validation in emulation environments.
• Support emulator build, compilation, partitioning, bring-up, and regression execution.
• Perform RTL debug, waveform analysis, and root-cause analysis of failing test scenarios.
• Validate DFX interactions with reset, clocking, power management, and subsystem integration flows.
• Execute large-scale SoC emulation regressions and drive bug closure.
• Develop regression automation, debug scripts, and reporting infrastructure using Python/TCL/Shell.
• Collaborate closely with DFX architects, RTL designers, DV teams, and SoC integration teams.

Required Skills

• 4+ years of experience in Design Verification, DFX Verification, Emulation, or SoC Validation.
• Strong experience with Palladium, Zebu, or Veloce emulation platforms.
• Strong SystemVerilog and UVM knowledge.
• Experience with:
• JTAG / IEEE 1149.x
• Boundary Scan
• Debug and Trace Architectures
• Test Access Mechanisms (TAM)
• SoC DFX Integration
• Strong RTL debugging skills using Verdi or equivalent debug tools.
• Experience analyzing emulator regressions and waveform debug.
• Proficiency in Python, TCL, Perl, or Shell scripting.

Preferred Skills

• SoC-level verification experience involving CPU, GPU, AI, Networking, or Server SoCs.
• Knowledge of AXI, AHB, APB, PCIe, DDR, NoC, and subsystem integration.
• Experience with firmware-driven or software-based validation in emulation.
• Familiarity with power-aware verification and low-power debug scenarios.

One-Line Requirement

Hands-on DFX DV Engineer with expertise in executing and debugging SoC-level DFX verification workloads on Palladium/Zebu/Veloce platforms, with strong SystemVerilog/UVM, RTL debug, and emulation regression experience.