SoC DFX Emulation Verification Engineer

UST; Penang; On-site; MYR 70,000 - 110,000; Full time

Job summary

UST in Penang, Malaysia is seeking a DFX Design Verification Engineer to execute and debug SoC-level DFX test suites on hardware emulation platforms such as Palladium, Zebu, or Veloce. You will validate DFX architecture, debug features, TAMs, and verify SoC integration in emulation environments.

Responsibilities include RTL debugging, waveform analysis, and regression development using Python/TCL/Shell. The role collaborates with DV teams and RTL designers to accelerate pre-silicon validation

Qualifications

• 4+ years of experience in Design Verification, DFX Verification, Emulation or SoC Validation.
• Experience with palladium, zebu, or veloce emulation platforms is required.
• Strong SystemVerilog and UVM knowledge.
• Familiarity with JTAG/IEEE 1149.x, Boundary Scan and TAM.

Responsibilities

• Execute and debug SoC-level DFX verification workloads on emulation platforms.
• Validate DFX features, test access mechanisms and debug infrastructure.
• Enable firmware/software-driven validation in emulation environments.
• Support emulator build, bring-up, and regression execution.
• Perform RTL debugging, waveform analysis, and root-cause analyses.
• Validate DFX interactions with clocking, reset, and power management flows.
• Drive large-scale emulation regressions and bug closure.
• Develop regression automation and reporting scripts using Python/TCL/Shell.
• Collaborate with DFX architects, RTL designers, DV teams, and integration teams.

Skills

Design Verification

DFX Verification

Emulation

SoC Validation

SystemVerilog

UVM

Palladium

Zebu

Veloce

Verdi

JTAG/IEEE 1149.x

Boundary Scan

Test Access Mechanisms (TAM)

Python scripting

TCL scripting

Shell scripting

Tools

Palladium

Zebu

Veloce

Verdi

Job description

UST in Penang, Malaysia is seeking a DFX Design Verification Engineer to execute and debug SoC-level DFX test suites on hardware emulation platforms such as Palladium, Zebu, or Veloce. You will validate DFX architecture, debug features, TAMs, and verify SoC integration in emulation environments.

Responsibilities include RTL debugging, waveform analysis, and regression development using Python/TCL/Shell. The role collaborates with DV teams and RTL designers to accelerate pre-silicon validation