Emulation & SoC Verification Engineer

UST Malaysia; Bayan Lepas; On-site; MYR 90,000 - 130,000; Full time

Job summary

UST Malaysia is seeking an experienced Design Verification Engineer to develop and execute verification plans for SoC/IP designs, with hands-on experience in simulation, debugging, and functional verification. The role includes supporting emulation/FPGA-based verification and writing C/C++ test code.

Applicants should have 4+ years in design verification and strong SystemVerilog/UVM knowledge, DV methodologies, and a solid background in emulation or FPGA environments.

Qualifications

• 4+ years of experience in Design Verification.
• Bachelor's/Master's degree in Electrical/Electronic Engineering, Computer Engineering, or related field.
• Strong experience in SystemVerilog/UVM and DV methodologies.
• Hands-on experience with Emulation or FPGA preferred.
• Proficiency in C/C++ programming.

Responsibilities

• Develop and execute verification plans for SoC/IP designs.
• Perform simulation, debugging, and functional verification.
• Support Emulation/FPGA-based verification.
• Write and debug C/C++ test code.
• Work closely with RTL/design teams to identify and resolve issues.

Skills

SystemVerilog

UVM

C/C++

DV methodologies

Education

Bachelor's/Master's degree in Electrical/Electronic Engineering, Computer Engineering, or related field

Tools

Emulation

FPGA

Job description

UST Malaysia is seeking an experienced Design Verification Engineer to develop and execute verification plans for SoC/IP designs, with hands-on experience in simulation, debugging, and functional verification. The role includes supporting emulation/FPGA-based verification and writing C/C++ test code.

Applicants should have 4+ years in design verification and strong SystemVerilog/UVM knowledge, DV methodologies, and a solid background in emulation or FPGA environments.