SoC/AI-SoC Verification Engineer (UVM/SystemVerilog)

XINPAL (MALAYSIA) SDN. BHD.; Bayan Lepas; Sur place; MYR 70 000 - 110 000; Plein temps

Résumé du poste

XinPal (MALAYSIA) SDN. BHD. in Bayan Lepas, Penang, is hiring a Design Verification Engineer to develop verification strategies for SoC and AI-SoC designs. You will build UVM-based testbenches, write test cases, and perform functional and coverage verification in collaboration with design teams.

We seek 1–3 years of relevant experience, a degree in Electrical/Computer Engineering, and strong SystemVerilog, C/C++, Python, and Makefile skills. Fresh graduates are welcome to apply.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 1–3 years of experience in block, subsystem, or full-chip verification; fresh graduates welcome.
• Proficient in SystemVerilog, C/C++, Python, and Makefile.

Responsabilités

• Develop and execute verification strategies for SoC and AI-SoC designs.
• Create UVM-based testbenches and write test cases.
• Perform functional and coverage verification and analyze results.
• Collaborate with design engineers to diagnose and resolve issues.
• Drive verification closure and mentor junior engineers.
• Participate in design and verification reviews and stay current with industry trends.

Connaissances

SystemVerilog

C/C++

Python

Makefile

Formation

Bachelors/Masters in EE/CE

Outils

GCC toolchain

C-SV DPI

Description du poste

XinPal (MALAYSIA) SDN. BHD. in Bayan Lepas, Penang, is hiring a Design Verification Engineer to develop verification strategies for SoC and AI-SoC designs. You will build UVM-based testbenches, write test cases, and perform functional and coverage verification in collaboration with design teams.

We seek 1–3 years of relevant experience, a degree in Electrical/Computer Engineering, and strong SystemVerilog, C/C++, Python, and Makefile skills. Fresh graduates are welcome to apply.