Design Verification Engineer

XINPAL (MALAYSIA) SDN. BHD.; Bayan Lepas; On-site; MYR 70,000 - 110,000; Full time

Job summary

XinPal (MALAYSIA) SDN. BHD. in Bayan Lepas, Penang, is hiring a Design Verification Engineer to develop verification strategies for SoC and AI-SoC designs. You will build UVM-based testbenches, write test cases, and perform functional and coverage verification in collaboration with design teams.

We seek 1–3 years of relevant experience, a degree in Electrical/Computer Engineering, and strong SystemVerilog, C/C++, Python, and Makefile skills. Fresh graduates are welcome to apply.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 1–3 years of experience in block, subsystem, or full-chip verification; fresh graduates welcome.
• Proficient in SystemVerilog, C/C++, Python, and Makefile.

Responsibilities

• Develop and execute verification strategies for SoC and AI-SoC designs.
• Create UVM-based testbenches and write test cases.
• Perform functional and coverage verification and analyze results.
• Collaborate with design engineers to diagnose and resolve issues.
• Drive verification closure and mentor junior engineers.
• Participate in design and verification reviews and stay current with industry trends.

Skills

SystemVerilog

C/C++

Python

Makefile

Education

Bachelors/Masters in EE/CE

Tools

GCC toolchain

C-SV DPI

Job description

XinPal Malaysia is part of an MNC headquartered in Singapore, specializing in delivering innovative technology solutions and supporting cutting-edge semiconductor projects. We are committed to building a high-performing team through innovation, collaboration, and continuous growth opportunities.

We are looking for a Design Verification Engineer in Bayan Lepas, Penang to develop and execute verification strategies for advanced SoC and AI-SoC designs. The role involves creating UVM-based testbenches, developing and executing test cases, performing functional and coverage verification, and collaborating closely with design engineers to identify and resolve design issues. You will also drive verification closure, contribute to process improvements, participate in design reviews, and support the delivery of high-quality semiconductor products.

Develop detailed verification plans based on design specifications and architectural requirements.

Create and maintain testbenches for complex digital designs using SystemVerilog and UVM (Universal Verification Methodology).

Write, debug, and execute test cases to verify functionality, performance, and power consumption of our SoC and AI-SoC products.

Collaborate with design engineers to identify, analyze, and resolve design issues.

Conduct coverage analysis and drive verification closure to ensure all functional requirements are met.

Mentor junior verification engineers, providing technical guidance and support.

Continuously improve verification processes and methodologies to enhance efficiency and effectiveness.

Participate in design and verification reviews, providing constructive feedback and recommendations.

Stay updated with the latest industry trends and advancements in verification techniques and tools.

Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related discipline.

1–3 years of experience in block, subsystem, or full-chip verification. Fresh graduates with strong academic projects are welcome to apply.

Proficient in SystemVerilog, C/C++, Python, and Makefile.

Good understanding of digital design and verification methodologies.

Familiar with one or more of the following:

• High-speed interfaces (PCIe, USB, SATA, Ethernet, MIPI)
• Memory systems (DDR, UFS, SD, eMMC)

Experience with CPU/DSP boot-up flow, GCC toolchain, or C-SV DPI is an advantage.

Knowledge of NPU boot-up flow, low-power verification, or low-power design is a plus.