Senior Design Verification Engineer: IP & Full-Chip Expert

Oppstar Berhad; Penang; On-site; MYR 60,000 - 90,000; Full time

Job summary

Oppstar Berhad in Penang, Malaysia is seeking a verification engineer to perform pre-Si verification on IP blocks and full-chip FPGA/ASIC designs.

You will define test plans, develop SystemVerilog/UVM testbenches and content, and debug and run regressions to deliver high-quality design validation. You will work closely with IP architects, logic design engineers, and design automation specialists to ensure robust verification flows.

Qualifications

• Experience in functional verification including test planning and bench development.
• 2

Responsibilities

• Define test plans and develop SystemVerilog/UVM testbenches.
• Debug and run regression to ensure high-quality validation.

Skills

Functional verification

SystemVerilog UVM

Constrained random verification

Assertion-based verification

Education

BSEE

MSEE

PhD

Tools

Cadence

Mentor Graphics

Synopsys

Job description

Oppstar Berhad in Penang, Malaysia is seeking a verification engineer to perform pre-Si verification on IP blocks and full-chip FPGA/ASIC designs.

You will define test plans, develop SystemVerilog/UVM testbenches and content, and debug and run regressions to deliver high-quality design validation. You will work closely with IP architects, logic design engineers, and design automation specialists to ensure robust verification flows.