Senior IC Verification Engineer — UVM/SystemVerilog

Bitdeer (NASDAQ: BTDR); Penang; Vor Ort; MYR 120.000 - 180.000; Vollzeit

Zusammenfassung

Bitdeer seeks a Design Verification Engineer to join its IC development team in Penang. You will develop verification environments and test plans to ensure correctness and performance of computer arithmetic IPs, collaborating with design and verification teams to deliver high‑quality silicon.

You will apply UVM, SystemVerilog, Verilog, and SVA in verification tasks, and use advanced tools like Palladium, HAPS, and Zebu for coverage-driven verification and regression.

Qualifikationen

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (or currently pursuing).
• Solid understanding of digital logic design and RTL development using Verilog or other HDL.
• Proficiency with AMBA bus protocols (AXI, AHB, APB).
• Hands‑on experience with RTL simulation, debugging, and waveform analysis using EDA tools (Synopsys, Cadence, or Siemens EDA / Mentor).
• Proficiency with SystemVerilog and modern verification methodologies such as UVM.
• Proficiency with formal verification tools (VC Formal or JasperGold) and main applications (FPV, DPV, etc).
• Familiarity with Linux/Unix environments and scripting for automation (e.g., Bash, C Shell, Perl, or Python).
• Experience using version control systems such as Git or SVN in a collaborative development environment.
• Good analytical and debugging skills, with the ability to identify and resolve RTL and functional issues.
• Strong communication skills in English, both written and verbal, with the ability to document verification results clearly.
• Self‑motivated, detail-oriented, and able to work effectively both independently and within a team environment.

Aufgaben

• Understand DUT architecture, interfaces and functional requirements.
• Bring up formal verification testbench, implement constraints and properties, run proofs, generate coverage.
• Collaborate with verification and design teams to define verification test plans.
• Implement test cases, stimuli, and patterns to validate DUT and corner cases.
• Execute simulations and analyze RTL issues with waveform tools.
• Run and maintain regression suites across development cycles.
• Monitor and improve coverage metrics for verification closure.
• Document test cases and results to support sign-off.
• Contribute to automation scripts and Verification IP to boost productivity.

Kenntnisse

RTL design

AMBA protocols

RTL simulation

SystemVerilog & UVM

Formal verification

Linux scripting

Git/SVN

Debugging

English communication

Self-motivation

Ausbildung

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

Synopsys

Cadence

Mentor Graphics

Palladium

HAPS

Zebu

Jobbeschreibung

Bitdeer seeks a Design Verification Engineer to join its IC development team in Penang. You will develop verification environments and test plans to ensure correctness and performance of computer arithmetic IPs, collaborating with design and verification teams to deliver high‑quality silicon.

You will apply UVM, SystemVerilog, Verilog, and SVA in verification tasks, and use advanced tools like Palladium, HAPS, and Zebu for coverage-driven verification and regression.