Senior Timing Closure Engineer - ASIC/SoC

UST Malaysia; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST Malaysia in Penang seeks a Senior STA Engineer with 6+ years of ASIC/SoC timing closure expertise to drive convergence from synthesis through signoff and deliver high-performance, low-power silicon on advanced nodes.

The role requires block-level and full-chip STA, constraint development, clock-domain analysis, and cross-functional collaboration with RTL, PD, DFT, and design teams to resolve timing violations and support tapeout readiness.

Qualifications

• 6+ years of experience in ASIC/SoC STA and timing closure.
• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering.
• Strong understanding of Static Timing Analysis fundamentals.

Responsibilities

• Perform block-level and full-chip STA, timing analysis, and signoff.
• Drive setup/hold closure across all modes and corners.
• Develop and validate timing constraints (SDC) and timing exceptions.
• Analyze and resolve timing violations related to clocks, data paths, and interfaces.
• Work closely with RTL, Physical Design, DFT, and Design teams to achieve timing closure.
• Support ECO implementation and timing verification.
• Perform timing signoff checks including SI, OCV/AOCV/POCV, crosstalk, and noise analysis.
• Debug timing issues and provide optimization recommendations for PPA improvements.
• Support tapeout activities and signoff readiness.

Skills

Static Timing Analysis

Timing constraints (SDC)

Clock Domain Crossing

OCV/AOCV/POCV

Crosstalk & SI

MCMM timing

Scripting (Tcl/Perl/Python)

Timing debugging

Cross-functional collaboration

Education

Electrical/Electronics/Computer Engineering

Tools

Tempus

Job description

UST Malaysia in Penang seeks a Senior STA Engineer with 6+ years of ASIC/SoC timing closure expertise to drive convergence from synthesis through signoff and deliver high-performance, low-power silicon on advanced nodes.

The role requires block-level and full-chip STA, constraint development, clock-domain analysis, and cross-functional collaboration with RTL, PD, DFT, and design teams to resolve timing violations and support tapeout readiness.