SoC Timing & DFT Signoff Engineer

Infinecs Systems Pvt. Ltd.; Malaysia; On-site; MYR 180,000 - 240,000; Full time

Job summary

Infinecs Systems Pvt. Ltd. in Malaysia is seeking a senior EDA engineer to focus on full-chip test mode timing signoff and SDC quality checks to ensure robust DFT implementation and timing closure.

The role supports cross-die STA activities, enhances STA automation flows, and works with Front-End and Physical Design teams to drive synthesis optimization, timing validation, and successful full-chip timing signoff.

Qualifications

• Master’s degree with 1 year or Bachelor’s with 3 years of experience.
• 5+ years of experience in STA, timing signoff, RTL design, or DFT timing analysis.
• Strong Verilog coding background for ASIC/RTL work.
• Exposure to CTS/ICC physical design flow and scan/BIST is a plus.

Responsibilities

• Study and implement cutting-edge test strategies for timing signoff.
• Develop and maintain DFT SDCs and timing checks.
• Support special timing checks and multi-voltage timing signoff.
• Enhance timing sign-off automation flows.
• Collaborate with Front End for synthesis optimization and SDC quality.
• Partner with Physical Design for smooth full-chip timing signoff.

Skills

Verilog RTL design

STA / timing signoff

DFT timing analysis

Scripting (Perl / Python / Tcl)

Cross-die STA collaboration

English / Mandarin communication

Education

Master's degree

Bachelor's degree

Tools

Design Compiler

Fusion Compiler

Primetime

Job description

Infinecs Systems Pvt. Ltd. in Malaysia is seeking a senior EDA engineer to focus on full-chip test mode timing signoff and SDC quality checks to ensure robust DFT implementation and timing closure.

The role supports cross-die STA activities, enhances STA automation flows, and works with Front-End and Physical Design teams to drive synthesis optimization, timing validation, and successful full-chip timing signoff.