Senior STA Engineer

UST Malaysia; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST Malaysia in Penang seeks a Senior STA Engineer with 6+ years of ASIC/SoC timing closure expertise to drive convergence from synthesis through signoff and deliver high-performance, low-power silicon on advanced nodes.

The role requires block-level and full-chip STA, constraint development, clock-domain analysis, and cross-functional collaboration with RTL, PD, DFT, and design teams to resolve timing violations and support tapeout readiness.

Qualifications

• 6+ years of experience in ASIC/SoC STA and timing closure.
• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering.
• Strong understanding of Static Timing Analysis fundamentals.

Responsibilities

• Perform block-level and full-chip STA, timing analysis, and signoff.
• Drive setup/hold closure across all modes and corners.
• Develop and validate timing constraints (SDC) and timing exceptions.
• Analyze and resolve timing violations related to clocks, data paths, and interfaces.
• Work closely with RTL, Physical Design, DFT, and Design teams to achieve timing closure.
• Support ECO implementation and timing verification.
• Perform timing signoff checks including SI, OCV/AOCV/POCV, crosstalk, and noise analysis.
• Debug timing issues and provide optimization recommendations for PPA improvements.
• Support tapeout activities and signoff readiness.

Skills

Static Timing Analysis

Timing constraints (SDC)

Clock Domain Crossing

OCV/AOCV/POCV

Crosstalk & SI

MCMM timing

Scripting (Tcl/Perl/Python)

Timing debugging

Cross-functional collaboration

Education

Electrical/Electronics/Computer Engineering

Tools

Tempus

Job description

We are seeking a Senior Static Timing Analysis (STA) Engineer with 6+ years of experience in ASIC/SoC timing closure. The candidate will be responsible for driving timing convergence from synthesis through signoff, ensuring high-performance and low-power silicon delivery across advanced technology nodes.

Key Responsibilities

• Perform block-level and full-chip STA, timing analysis, and signoff.
• Drive setup/hold closure across all modes and corners.
• Develop and validate timing constraints (SDC) and timing exceptions.
• Analyze and resolve timing violations related to clocks, data paths, and interfaces.
• Work closely with RTL, Physical Design, DFT, and Design teams to achieve timing closure.
• Support ECO implementation and timing verification.
• Perform timing signoff checks including SI, OCV/AOCV/POCV, crosstalk, and noise analysis.
• Debug timing issues and provide optimization recommendations for PPA improvements.
• Support tapeout activities and signoff readiness.

Required Qualifications

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering.
• 6+ years of experience in ASIC/SoC STA and timing closure.
• Strong understanding of:
• Static Timing Analysis fundamentals
• Timing Constraints (SDC)
• Clock Domain Crossing (CDC)
• OCV/AOCV/POCV methodologies
• Crosstalk and Signal Integrity analysis
• MCMM timing analysis
• Hands-on experience with:
• Tempus (preferred)
• Experience with advanced technology nodes ("16nm and below preferred").
• Proficiency in Tcl, Perl, or Python scripting.

Preferred Qualifications

• Experience with full-chip signoff and tapeout.
• Knowledge of Physical Design flow and ECO methodologies.
• Familiarity with low-power designs (UPF/CPF).
• Experience in 7nm, 5nm, or advanced FinFET technologies.

Key Skills

• Strong timing debugging and analysis skills.
• Excellent problem-solving and analytical abilities.
• Ability to work independently and drive timing closure.
• Effective communication and cross-functional collaboration.