SoC DFX Timing Engineer

Infinecs Systems Pvt. Ltd.; Malaysia; On-site; MYR 180,000 - 240,000; Full time

Job summary

Infinecs Systems Pvt. Ltd. in Malaysia is seeking a senior EDA engineer to focus on full-chip test mode timing signoff and SDC quality checks to ensure robust DFT implementation and timing closure.

The role supports cross-die STA activities, enhances STA automation flows, and works with Front-End and Physical Design teams to drive synthesis optimization, timing validation, and successful full-chip timing signoff.

Qualifications

• Master’s degree with 1 year or Bachelor’s with 3 years of experience.
• 5+ years of experience in STA, timing signoff, RTL design, or DFT timing analysis.
• Strong Verilog coding background for ASIC/RTL work.
• Exposure to CTS/ICC physical design flow and scan/BIST is a plus.

Responsibilities

• Study and implement cutting-edge test strategies for timing signoff.
• Develop and maintain DFT SDCs and timing checks.
• Support special timing checks and multi-voltage timing signoff.
• Enhance timing sign-off automation flows.
• Collaborate with Front End for synthesis optimization and SDC quality.
• Partner with Physical Design for smooth full-chip timing signoff.

Skills

Verilog RTL design

STA / timing signoff

DFT timing analysis

Scripting (Perl / Python / Tcl)

Cross-die STA collaboration

English / Mandarin communication

Education

Master's degree

Bachelor's degree

Tools

Design Compiler

Fusion Compiler

Primetime

Job description

This role is focused on full-chip test mode timing signoff and SDC quality checks to ensure robust DFT implementation and timing closure. The engineer will support cross-die STA activities, enhance STA automation flows, and work closely with Front-End and Physical Design teams to drive synthesis optimization, timing validation, and successful full-chip timing signoff. We are looking for a collaborative team player with strong Verilog RTL design knowledge and experience, while exposure to synthesis, scan/BIST, multi-power timing signoff, and STA methodologies would be highly advantageous.

Responsibilities

• Cutting-edge test strategies study and implementation.
• DFT sdc development and maintenance.
• Support special timing check and multi-voltage timing check.
• Timing sign-off automation flow enhancement.
• Co-work with Front End design team for synthesis optimization and sdc quality check.
• Co-work with Physical design team for full chip smooth timing signoff.

Requirements

• Master’s degree with 1 year or Bachelor with 3 years’ experience at least.
• Minimum 5 years of experience in STA, timing signoff, synthesis, RTL design, DFT timing analysis, or physical design environments.
• Solid background on process, device or ASIC design.
• Strong technical background in Verilog coding.
• Experience in Design Compiler, Fusion Compiler and Primetime EDA tools will be a plus.
• Good knowledge on DFT Scan/BIST will be a strong plus.
• Good knowledge on CTS and ICC physical design flow will be a strong plus.
• Proven knowledge and expertise on two or more fields of SCAN, MBIST, RTL design, STA and DV.
• Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus.
• Good communication skills (both English and Mandarin) and self-driven, willing to learn/share.