Senior ASIC Physical Design Engineer - PPA & Tapeout Lead

UST Malaysia; Penang; On-site; MYR 120,000 - 300,000; Full time

Job summary

UST Malaysia is seeking a Senior Physical Design Engineer with 8+ years of ASIC/SoC experience to lead full-chip and block-level PD in Penang. You will drive floorplanning, placement, CTS, routing, timing closure and physical signoff for advanced nodes.

Work with RTL, DFT, STA and verification teams to achieve design closure while optimizing area, power and performance and supporting tapeout and silicon bring-up.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering.
• 8+ years hands-on ASIC/SoC Physical Design experience.
• Expertise in Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Verification.
• Proficiency with Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, and Calibre.

Responsibilities

• Lead end-to-end Physical Design from netlist to GDSII.
• Drive floorplanning, power planning, placement, CTS, routing, and signoff.
• Analyze timing, congestion, power, SI, and DRC/LVS issues.
• Collaborate with RTL, STA, DFT, and verification teams to close design.

Skills

ASIC/SoC PD

Floorplanning

Power Planning

Placement & Optimization

CTS

Timing Closure

Routing

Physical Verification

Scripting (Tcl/Python)

Collaboration

Education

Bachelor's or Master's in Electrical/Electronics/CE

Tools

Cadence Innovus

Synopsys ICC2/Fusion Compiler

PrimeTime

Calibre

Job description

UST Malaysia is seeking a Senior Physical Design Engineer with 8+ years of ASIC/SoC experience to lead full-chip and block-level PD in Penang. You will drive floorplanning, placement, CTS, routing, timing closure and physical signoff for advanced nodes.

Work with RTL, DFT, STA and verification teams to achieve design closure while optimizing area, power and performance and supporting tapeout and silicon bring-up.